AM79C970AKCW AMD [Advanced Micro Devices], AM79C970AKCW Datasheet - Page 108

• Manufacturer Part Number: AM79C970AKCW
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: AMD [Advanced Micro Devices]

0
PCI Status Register (Offset 06h)
The PCI Status register is a 16-bit register that contains
status information for the PCI bus related events. It is lo-
cated at offset 06h in the PCI Configuration Space.
Bit
15
108
AMD
PERR
IOEN
Name
address so that the device does
not claim cycles not intended
for it.
MEMEN is cleared by H_RESET
and is not effected by S_RESET
or by setting the STOP bit.
I/O Space access enable. The
PCnet-PCI II controller will ignore
all I/O accesses when IOEN is
cleared. The host must set IOEN
before the first I/O access to the
device. The PCI I/O Base
Address
programmed with a valid I/O ad-
dress before setting IOEN.
IOEN is cleared by H_RESET
and is not effected by S_RESET
or by setting the STOP bit.
Description
Parity Error. PERR is set when
the PCnet-PCI II controller de-
tects a parity error.
The PCnet-PCI II controller sam-
ples the AD[31:0], C/BE[3:0] and
the PAR lines for a parity error at
the following times:
In slave mode, during the
address phase of any PCI
bus command.
In slave mode, for all I/O, mem-
ory
commands
PCnet-PCI II controller when
data is transferred (TRDY and
IRDY are asserted).
In master mode, during the
data phase of all memory
read commands.
In master mode, during the data
phase of the memory write com-
mand, the PCnet-PCI II controller
sets the PERR bit if the target re-
ports a data parity error by as-
serting the PERR signal.
PERR is not effected by the state
of the Parity Error Response en-
able bit (PCI Command register,
bit 6).
PERR is set by the PCnet-PCI II
controller and cleared by writing
a ONE. Writing a ZERO has no
effect. PERR is cleared by
H_RESET and is not affected by
and
register
configuration
that
select
must
P R E L I M I N A R Y
write
Am79C970A
the
be
14
13
12
11
10–9 DEVSEL
8
DATAPERR
RMABORT
RTABORT
STABORT
SERR
S_RESET or by setting the
STOP bit.
Signaled SERR. SERR is set
when the PCnet-PCI II controller
detects an address parity error,
and both SERREN and PERREN
(PCI Command register, bits 8
and 6) are set.
SERR is set by the PCnet-PCI II
controller and cleared by writing
a ONE. Writing a ZERO has no
effect. SERR is cleared by
H_RESET and is not affected by
S_RESET or by setting the
STOP bit.
Received
RMABORT is set when the
PCnet-PCI II controller termi-
nates a master cycle with a mas-
ter abort sequence.
RMABORT
PCnet-PCI
cleared by writing a ONE. Writing
a
RMABORT
H_RESET and is not affected by
S_RESET or by setting the
STOP bit.
Received
RTABORT is set when a target
terminates a PCnet-PCI II con-
troller master cycle with a target
abort sequence.
RTABORT
PCnet-PCI
cleared by writing a ONE. Writing
a
RTABORT
H_RESET and is not affected by
S_RESET or by setting the
STOP bit.
Send Target Abort. Read as
ZERO, write operations have
no effect. The PCnet-PCI II con-
troller will never terminate a
slave access with a target
abort sequence.
STABORT is read only.
Device Select timing. DEVSEL is
set to 01b (medium), which
means that the PCnet-PCI II
controller will assert DEVSEL
two clock periods after FRAME
is asserted.
DEVSEL is read only.
Data
DATAPERR is set when the
PCnet-PCI II controller is the cur-
rent bus master and it detects a
ZERO
ZERO
Parity
II
II
is
has
has
is
is
Master
is
Target
Error
controller
controller
set
set
cleared
cleared
no
no
detected.
by
by
effect.
effect.
Abort.
Abort.
and
and
the
the
by
by