AM79C970AKCW AMD [Advanced Micro Devices], AM79C970AKCW Datasheet - Page 68

• Manufacturer Part Number: AM79C970AKCW
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: AMD [Advanced Micro Devices]

controller, then the software must not read ahead to the
next descriptor. The software should wait at a descriptor
it does not own until the PCnet-PCI II controller sets
OWN to ZERO to release ownership to the software.
(When LAPPEN (CSR3, bit 5) is set to ONE, this rule is
modified. See the LAPPEN description.)
At initialization, the PCnet-PCI II controller reads the
base address of both the transmit and receive descriptor
rings into CSRs for use by the PCnet-PCI II controller
during subsequent operations.
68
AMD
RLE
TLE
IADR[31:16]
CSR2
LADRF[47:32]
LADRF[63:48]
LADRF[31:16]
RES
RES
LADRF[15:0]
PADR[31:16]
PADR[47:32]
Initialization
RDRA[15:0]
PADR[15:0]
TDRA[15:0]
Block
MOD
RDRA[23:16]
TDRA[23:16]
IADR[15:0]
CSR1
Figure 32. 16-Bit Software Model
P R E L I M I N A R Y
Buffers
Buffers
Am79C970A
Rcv
Xmt
1st desc.
start
The following figure illustrates the relationship between
the initialization base address, the initialization block,
the receive and transmit descriptor ring base ad-
dresses, the receive and transmit descriptors and the
receive and transmit data buffers, when SSIZE32 is
cleared to ZERO.
Note that the value of CSR2, bits 15–8 is used as the
upper 8-bits for all memory addresses during bus
master transfers.
RMD0
1st desc.
start
TMD
Buffer
Buffer
Data
Data
1
1
RMD
N
Rcv Descriptor
TMD
M
Xmt Descriptor
Ring
RMD
Buffer
Buffer
N
TMD
Data
Data
Ring
2
2
M
RMD
N
TMD
M
2nd
desc.
2nd
desc.
RMD0
N
TMD
M
•
Buffer
Buffer
Data
Data
•
•
M
N
•
•
•
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