AM79C970AKCW AMD [Advanced Micro Devices], AM79C970AKCW Datasheet - Page 24

• Manufacturer Part Number: AM79C970AKCW
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: AMD [Advanced Micro Devices]

H_RESET (HARDWARE_RESET). RST must be held
for a minimum of 30 clock periods. While in the H_RE-
SET state, the PCnet-PCI II controller will disable or
deassert all outputs. RST may be asynchronous to CLK
when asserted or deasserted. It is recommended that
the deassertion be synchronous to guarantee clean and
bounce free edge.
When RST is active, NAND tree testing is enabled. All
PCI interface pins are in input mode. The result of the
NAND tree testing can be observed on the NOUT
output (pin 62).
SERR
System Error
During any slave transaction, the PCnet-PCI II controller
asserts SERR when it detects an address parity error
and reporting of the error is enabled by setting PERREN
(PCI Command register, bit 6) and SERREN (PCI Com-
mand register, bit 8) to ONE.
By default SERR is an open-drain output. For compo-
nent test it can be programmed to be an active-high to-
tem-pole output.
When RST is active, SERR is an input for NAND
tree testing.
STOP
Stop
In slave mode, the PCnet-PCI II controller drives the
STOP signal to inform the bus master to stop the current
transaction. In bus master mode, the PCnet-PCI II con-
troller checks STOP to determine if the target wants to
disconnect the current transaction.
When RST is active, STOP is an input for NAND
tree testing.
TRDY
Target Ready
TRDY indicates the ability of the target of the transaction
to complete the current data phase. TRDY is used in
conjunction with IRDY. Wait states are inserted until
both IRDY and TRDY are asserted simultaneously. A
data phase is completed on any clock when both IRDY
and TRDY are asserted.
When the PCnet-PCI II controller is a bus master, it
checks TRDY during all read data phases to determine if
valid data is present on AD[31:0]. During all write data
phases the device checks TRDY to determine if the tar-
get is ready to accept the data.
When the PCnet-PCI II controller is the target of a trans-
action, it asserts TRDY during all read data phases to in-
dicate that valid data is present on AD[31:0]. During all
write data phases the device asserts TRDY to indicate
that it is ready to accept the data.
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AMD
Input/Output
Input/Output
Input/Output
P R E L I M I N A R Y
Am79C970A
When RST is active, TRDY is an input for NAND
tree testing.
Board Interface
LED1
LED1
This output is designed to directly drive an LED. By de-
fault, LED1 indicates receive activity on the network.
This pin can also be programmed to indicate other
network status (see BCR5). The LED1 pin polarity is
programmable, but by default, it is active LOW.
Note that the LED1 pin is multiplexed with the EESK and
SFBD pins.
LED2
LED2
This output is designed to directly drive an LED. By de-
fault, LED2 indicates correct receive polarity on the
10BASE-T interface. This pin can also be programmed
to indicate other network status (see BCR6). The LED2
pin polarity is programmable, but by default, it is
active LOW.
Note that the LED2 pin is multiplexed with the
SRDCLK pin.
LED3
LED3
This output is designed to directly drive an LED. By de-
fault, LED3 indicates transmit activity on the network.
This pin can also be programmed to indicate other net-
work status (see BCR7). The LED3 pin polarity is pro-
grammable, but by default, it is active LOW.
Note that the LED3 pin is multiplexed with the EEDO
and SRD pins.
Special attention must be given to the external circuitry
attached to this pin. When this pin is used to drive an
LED while an EEPROM is used in the system, then buff-
ering is required between the LED3 pin and the LED cir-
cuit. If an LED circuit were directly attached to this pin, it
would create an I
by the serial EEPROM attached to this pin. If no
EEPROM is included in the system design, then the
LED3 signal may be directly connected to an LED with-
out buffering. For more details regarding LED connec-
tion, see the section “LED Support”.
SLEEP
Sleep
When SLEEP is asserted, the PCnet-PCI II controller
performs an internal system reset of the S_RESET type
and then proceeds into a power savings mode. All
PCnet-PCI II controller outputs will be placed in their
normal reset condition. All PCnet-PCI II controller inputs
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requirement that could not be met
Output
Output
Output
Input