AM79C970AKCW AMD [Advanced Micro Devices], AM79C970AKCW Datasheet - Page 156

• Manufacturer Part Number: AM79C970AKCW
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: AMD [Advanced Micro Devices]

12–5
4
3
2
156
(BCR19[3])
EEDET
Value
AMD
0
0
1
1
RES
EEN
RES
ECS
Connected?
EEPROM
Yes
Yes
No
No
Reserved locations. Written as
ZEROs, read as undefined.
EEPROM port enable. When this
bit is set to ONE, it causes the
values of ECS, ESK, and EDI to
be driven onto the EECS, EESK,
and EEDI pins, respectively. If
EEN is cleared to ZERO and no
EEPROM
currently active, then EECS will
be driven LOW and the EESK
and EEDI pins change their
function to LED1 and LNKST and
are controlled by BCR5 and
BCR4, respectively.
Read accessible always. Write
accessible only when either the
STOP or the SPND bit is set.
EEN is cleared to ZERO by
H_RESET and is unaffected by
S_RESET or by setting the
STOP bit.
Reserved location. Written as
ZERO and read as undefined.
EEPROM Chip Select. This bit is
used to control the value of the
EECS pin of the Microwire inter-
face when the EEN bit is set to
ONE and the PREAD bit is
cleared to ZERO. If EEN is set to
ONE and PREAD is cleared to
ZERO and ECS is set to ONE,
then the EECS pin will be forced
to a HIGH level at the rising edge
of the next clock following bit pro-
gramming. If EEN is set to ONE
and PREAD is cleared to ZERO
EEPROM read operation is attempted.
Entire read sequence will occur,
checksum failure will result, PVALID
is cleared to ZERO.
EEPROM read operation is attempted.
Entire read sequence will occur,
checksum operation will pass, PVALID
EEPROM read operation is attempted.
Entire read sequence will occur,
checksum failure will result, PVALID
is cleared to ZERO.
EEPROM read operation is attempted.
Entire read sequence will occur,
checksum operation will pass, PVALID
is set to ONE.
is set to ONE.
read
Result if PREAD is Set to ONE
function
Table 33. EEDET Setting
P R E L I M I N A R Y
Am79C970A
is
1
ESK
Result of Automatic EEPROM Read
Operation Following H_RESET
First TWO EESK clock cycles are
operation is aborted and PVALID
is cleared to ZERO.
First TWO EESK clock cycles are
cleared to ZERO.
Entire read sequence will occur,
checksum failure will result, PVALID is
EEPROM read operation is attempted.
Entire read sequence will occur,
checksum operation will pass, PVALID
is set to ONE.
generated, then EEPROM read
generated, then EEPROM read
operation is aborted and PVALID is
EEPROM read operation is attempted.
cleared to ZERO.
and ECS is cleared to ZERO,
then the EECS pin will be forced
to a LOW level at the rising edge
of the next clock following bit pro-
gramming. ECS has no effect on
the output value of the EECS pin
unless the PREAD bit is cleared
to ZERO and the EEN bit is set
to ONE.
Read accessible always. Write
accessible only when either the
STOP or the SPND bit is set.
ECS is cleared to ZERO by
H_RESET and is not affected by
S_RESET or by setting the
STOP bit.
EEPROM Serial Clock. This bit
and the EDI/EDO bit are used to
control host access to the
EEPROM. Values programmed
to this bit are placed on to the
EESK pin at the rising edge of the
next clock following bit program-
ming, except when the PREAD
bit is set to ONE or the EEN bit is
cleared to ZERO. If both the ESK
bit and the EDI/EDO bit values
are changed during one BCR19
write operation while EEN is set
to ONE, then setup and hold
times of the EEDI pin value with
respect to the EESK signal edge
are not guaranteed.
ESK has no effect on the EESK
pin unless the PREAD bit is
cleared to ZERO and the EEN bit
is set to ONE.