AM79C970AKCW AMD [Advanced Micro Devices], AM79C970AKCW Datasheet - Page 132

• Manufacturer Part Number: AM79C970AKCW
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: AMD [Advanced Micro Devices]

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AMD
SSIZE32
(SWSTYLE,
this register).
Read
CSRPCNET is read only. Write
operations
CSRPCNET will be set after
H_RESET (since SWSTYLE de-
faults to ZERO) and is not af-
fected by S_RESET or by setting
the STOP bit.
32-Bit Software Size. When set,
this
PCnet-PCI II controller utilizes
32-bit software structures for the
initialization block and the trans-
mit and receive descriptor en-
tries. When cleared, this bit
indicates that the PCnet-PCI II
controller utilizes 16-bit software
structures for the initialization
block and the transmit and
receive descriptor entries. In this
mode the PCnet-PCI II controller
is backwards compatible with
the Am79C90 C-LANCE and
Am79C960 PCnet-ISA.
The value of SSIZE32 is deter-
mined by the PCnet-PCI II con-
troller according to the setting of
the Software Style (SWSTYLE,
bits 7–0 of this register).
Read
SSIZE32 is read only. Write
operations
SSIZE32 will be cleared after
H_RESET (since SWSTYLE de-
faults to ZERO) and is not
affected by S_RESET or by set-
ting the STOP bit.
If SSIZE32 is cleared to ZERO,
then bits IADR[31:24] of CSR2
will be used to generate values
for the upper 8 bits of the 32 bit
address
accesses
PCnet-PCI II controller. This
action is required, since the
16-bit software structures will
bit
accessible
accessible
bus
indicates
initiated
will
will
bits
during
be
be
that
7–0
by
P R E L I M I N A R Y
ignored.
ignored.
always.
always.
master
Am79C970A
the
the
of
7–0 SWSTYLE
yield only 24 bits of address for
PCnet-PCI
master accesses.
If SSIZE32 is set to ONE, then
the software structures that are
common to the PCnet-PCI II con-
troller and the host system will
supply a full 32 bits for each ad-
dress pointer that is needed by
the PCnet-PCI II controller for
performing master accesses.
The value of the SSIZE32 bit has
no effect on the drive of the upper
8 address bits. The upper 8 ad-
dress pins are always driven, re-
gardless of the state of the
SSIZE32 bit.
Note that the setting of the
SSIZE32 bit has no effect on the
width for I/O accesses. I/O
access width is determined by
the state of the DWIO bit
(BCR18, bit 7).
Software Style register. The
value in this register determines
the style of register and memory
resources that shall be used by
the PCnet-PCI II controller. The
Software Style selection will af-
fect the interpretation of a few
bits within the CSR space, the or-
der of the descriptor entries and
the width of the descriptors and
initialization block entries.
All PCnet-PCI II controller CSR
bits and BCR bits and all descrip-
tor, buffer and initialization block
entries not cited in the table
above are unaffected by the soft-
ware style selection.
Read/Write
when either the STOP or the
SPND bit is set. The SWSTYLE
register will contain the value 00h
following H_RESET and will be
unaffected by S_RESET or by
setting the STOP bit.
II
accessible
controller
only
bus