AM79C970AKCW AMD [Advanced Micro Devices], AM79C970AKCW Datasheet - Page 50

• Manufacturer Part Number: AM79C970AKCW
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: AMD [Advanced Micro Devices]

Target Abort
The figure below shows a target abort sequence. The
target asserts DEVSEL for one clock. It then deasserts
DEVSEL and asserts STOP on clock 4. A target can use
the target abort sequence to indicate that it cannot serv-
ice the data transfer and that it does not want the
transaction to be retried. Additionally, the PCnet-PCI II
controller cannot make any assumption about the suc-
cess of the previous data transfers in the current trans-
action. The PCnet-PCI II controller terminates the
current transfer with the deassertion of FRAME on clock
5 and of IRDY one clock cycle later. It finally releases the
bus on clock 6.
Since data integrity is not guaranteed, the PCnet-PCI II
controller cannot recover from a target abort event. The
PCnet-PCI II controller will reset all CSR locations to
their STOP_RESET values. The BCR and PCI
50
AMD
DEVSEL
FRAME
TRDY
STOP
IRDY
C/BE
REQ
GNT
PAR
CLK
AD
1
DEVSEL is sampled
Figure 19. Target Abort
P R E L I M I N A R Y
ADDR
0111
2
Am79C970A
PAR
3
DATA
0000
configuration registers will not be cleared. Any on-going
network transmission is terminated in an orderly se-
quence. If less than 512 bits have been transmitted onto
the network, the transmission will be terminated imme-
diately, generating a runt packet. If 512 bits or more
have been transmitted, the message will have the cur-
rent FCS inverted and appended at the next byte bound-
ary to guarantee an FCS error is detected at the
receiving station.
RTABORT (PCI Status register, bit 12) will be set to indi-
cate that the PCnet-PCI II controller has received a tar-
get abort. In addition, SINT (CSR5, bit 11) will be set to
ONE. When SINT is set, INTA is asserted if the enable
bit SINTE (CSR5, bit 10) is set to ONE. This mechanism
can be used to inform the driver of the system error. The
host can read the PCI Status register to determine the
exact cause of the interrupt.
4
PAR
5
6
19436A-22