AM79C970AKCW AMD [Advanced Micro Devices], AM79C970AKCW Datasheet - Page 136

• Manufacturer Part Number: AM79C970AKCW
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: AMD [Advanced Micro Devices]

9–8 XMTFW[1:0]
136
Table 28. Transmit Watermark Programming
Table 27. Transmit Start Point Programming
AMD
XMTFW[1:0]
XMTSP[1:0]
00
01
10
11
00
01
10
11
starts trying to transmit. When
the entire frame is in the FIFO,
transmission attempts will start
regardless
XMTSP. If the network interface
is operating in half-duplex mode,
regardless of XMTSP, the FIFO
will not internally overwrite its
data until at least 64 bytes (or the
entire frame if shorter than 64
bytes) have been transmitted
onto the network. This ensures
that for collisions within the slot
time window, transmit data need
not be reloaded into the transmit
FIFO, and retries will be handled
autonomously by the MAC. If the
Disable Retry feature is enabled,
or if the network is operating in
full-duplex mode, the PCnet-PCI
II controller can overwrite the be-
ginning of the frame as soon as
the data is transmitted, because
no collision handling is required
in these modes.
Read/Write
when either the STOP or the
SPND bit is set. XMTSP is set to
a value of 01b (64 bytes) after
H_RESET or S_RESET and
is unaffected by setting the
STOP bit.
Transmit
XMTFW controls the point at
which transmit DMA is re-
quested. Transmit DMA is re-
quested when the number of
bytes specified by XMTFW can
be written to the transmit FIFO.
Read/Write
when either the STOP or the
SPND bit is set. XMTFW is set to
Byte Spaces Available
Bytes Written
FIFO
of
Reserved
accessible
accessible
128
248
128
64
16
64
the
8
Watermark.
value
P R E L I M I N A R Y
only
only
Am79C970A
in
7–0 DMATC[7:0]
a value of 00b (16 bytes)
after H_RESET or S_RESET
and is unaffected by setting the
STOP bit.
DMA
DMAPLUS (CSR4, bit 14) is
cleared to ZERO, this counter
contains the maximum number
of FIFO read or write data phases
the PCnet-PCI II controller will
perform during a single bus mas-
tership period, if not preempted.
The DMA Transfer Counter is not
used to limit the number of data
phases during initialization block
or descriptor transfers. A value of
ZERO will be interpreted as one
data phase. If DMAPLUS is set to
ONE, the DMA Transfer Counter
is disabled, and the PCnet-PCI II
controller will try to transfer data
as long as the transmit FIFO is
not full or as long as the receive
FIFO is not empty.
When the PCnet-PCI II controller
is preempted and the last data
phase has finished, DMATC will
freeze. It will continue counting
down when the PCnet-PCI II
controller is granted bus owner-
ship again and continues with the
data transfers.
DMATC should not be enabled
when the PCnet-PCI II controller
is used in a PCI bus application.
The PCI Latency Timer should be
the only entity governing the time
the PCnet-PCI II controller has
control over the bus.
Read/Write
when either the STOP or the
SPND bit is set. Note that the
read operation will yield the value
of the run-time copy of the DMA
Transfer Counter and not the
register that holds the pro-
grammed value. Most read op-
erations will yield a value of
ZERO, because the run-time
counter is only reloaded with
the programmed value at the be-
ginning of a new bus mastership
period.
Counter is set to a value of
16 (10h) after H_RESET or
S_RESET and is unaffected by
setting the STOP bit.
Transfer
The
accessible
DMA
Counter.
Transfer
only
If