AM79C970AKCW AMD [Advanced Micro Devices], AM79C970AKCW Datasheet - Page 112

• Manufacturer Part Number: AM79C970AKCW
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: AMD [Advanced Micro Devices]

PCI MIN_GNT Register (Offset 3Eh)
The PCI MIN_GNT register is an 8-bit register that
specifies the minimum length of a burst period that the
PCnet-PCI II controller needs to keep up with the net-
work activity. The length of the burst period is calculated
assuming a clock rate of 33 MHz. The register value
specifies the time in units of 1/4 ms. The PCI MIN_GNT
register is an alias of BCR22, bits 7–0. The default value
for MIN_GNT is 06h, which corresponds to a minimum
grant of 1.5 s. One and a half s is the time it takes the
PCnet-PCI II controller to read/write 64 bytes. (16
DWord transfers in burst mode with one extra wait state
per data phase inserted by the target.)
Note that the default is only a typical value. This calcula-
tion also does not take into account any descriptor ac-
cesses.
The host should use the value in this register to deter-
mine the setting of the PCI Latency Timer register.
The PCI MIN_GNT register is located at offset 3Eh in the
PCI Configuration Space. It is read only.
PCI MAX_LAT Register (Offset 3Fh)
The PCI MAX_LAT register is an 8-bit register that
specifies
PCnet-PCI II controller can sustain without causing
problems to the network activity. The register value
specifies the time in units of 1/4 microseconds. The
MAX_LAT register is an alias of BCR22, bits 15–8.
The default value for MAX_LAT is FFh, which corre-
sponds to a maximum latency of 63.75 s. The actual
maximum latency the PCnet-PCI II controller can
handle is 153.6 s, which is also the value for the bus
time-out (see CSR100).
The host should use the value in this register to deter-
mine the setting of the PCI Latency Timer register.
The PCI MAX_LAT register is located at offset 3Fh in the
PCI Configuration Space. It is read only.
RAP Register
The RAP (Register Address Pointer) register is used to
gain access to CSR and BCR registers on board the
PCnet-PCI II controller. The RAP contains the address
of a CSR or BCR.
As an example of RAP use, consider a read access to
CSR4. In order to access this register, it is necessary to
first load the value 0004h into the RAP by performing a
write access to the RAP offset of 12h (12h when WIO
mode has been selected, 14h when DWIO mode has
been selected). Then a second access is performed,
this time to the RDP offset of 10h (for either WIO or
DWIO mode). The RDP access is a read access, and
since RAP has just been loaded with the value of 0004h,
the RDP read will yield the contents of CSR4. A read of
the BDP at this time (offset of 16h when WIO mode has
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AMD
the
maximum
arbitration
latency
P R E L I M I N A R Y
Am79C970A
the
been selected, 1Ch when DWIO mode has been se-
lected) will yield the contents of BCR4, since the RAP is
used as the pointer into both BDP and RDP space.
RAP: Register Address Port
Bit
31–16 RES
15–8
7–0
A write access to undefined CSR or BCR locations may
cause unexpected reprogramming of the PCnet-PCI II
controller control registers. A read access will yield
undefined values.
Read/Write accessible always. RAP is cleared by
H_RESET or S_RESET and is unaffected by setting the
STOP bit.
Control and Status Registers
The CSR space is accessible by performing accesses to
the RDP (Register Data Port). The particular CSR that is
read or written during an RDP access will depend upon
the current setting of the RAP. RAP serves as a pointer
into the CSR space.
CSR0: PCnet-PCI II Controller Controller Status
Register
Bit
31–16 RES
15
14
BABL
Name
Name
RES
RAP
ERR
Description
Reserved locations. Written as
ZEROs and read as undefined.
Reserved locations. Read and
written as ZEROs.
Register Address Port. The value
of these 8 bits determines which
CSR or BCR will be accessed
when an I/O access to the
RDP or BDP port, respectively,
is performed.
Description
Certain bits in CSR0 indicate the
cause of an interrupt. The regis-
ter is designed so that these indi-
cator bits are cleared by writing
ONEs to those bit locations. This
means that the software can read
CSR0
value just read to clear the
interrupt condition.
Reserved locations. Written as
ZEROs and read as undefined.
Error is set by the ORing of
BABL, CERR, MISS, and MERR.
ERR remains set as long as any
of the error flags are true.
Read accessible always. ERR is
read
are ignored.
Babble is a transmitter time-out
error. BABL is set by the
only.
and
Write
write
operations
back
the