AM79C970AKCW AMD [Advanced Micro Devices], AM79C970AKCW Datasheet - Page 42

• Manufacturer Part Number: AM79C970AKCW
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: AMD [Advanced Micro Devices]

Master Bus Interface Unit
The master bus interface unit (BIU) controls the
acquisition of the PCI bus and all accesses to the
initialization block, descriptor rings and the receive and
Bus Acquisition
The PCnet-PCI II controller microcode will determine
when a DMA transfer should be initiated. The first step in
any PCnet-PCI II controller bus master transfer is to
acquire ownership of the bus. This task is handled by
synchronous logic within the BIU. Bus ownership is re-
quested with the REQ signal and ownership is granted
by the arbiter through the GNT signal.
Figure 12 shows the PCnet-PCI II controller bus
acquisition. REQ is asserted and the arbiter returns
GNT while another bus master is transferring data. The
PCnet-PCI II controller waits until the bus is idle
(FRAME and IRDY deasserted) before it starts driving
AD[31:0] and C/BE[3:0] on clock 5. FRAME is asserted
at clock 5 indicating a valid address and command on
AD[31:0] and C/BE[3:0]. The PCnet-PCI II controller
does not use address stepping which is reflected by
42
C[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
AMD
Command
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Configuration Read
Configuration Write
Memory Read Multiple
Dual Address Cycle
Memory Read Line
Memory Write Invalidate
Table 3. Master Commands
P R E L I M I N A R Y
Am79C970A
Use
Not Used
Not Used
Not Used
Not Used
Read of the Initialization Block and Descriptor Rings
Read of the Transmit Buffer in Non-burst Mode
Write to the Descriptor Rings and to the Receive Buffer
Not Used
Not Used
Read of the Transmit Buffer in Burst Mode
Not Used
Read of the Transmit Buffer in Burst Mode
Not Used
transmit buffer memory. The table below shows the us-
age of PCI commands by the PCnet-PCI II controller in
master mode.
ADSTEP (bit 7) in the PCI Command register being
hardwired to ZERO.
In burst mode, the deassertion of REQ depends on the
setting of EXTREQ (BCR18, bit 8). If EXTREQ is
cleared to ZERO , REQ is deasserted at the same time
as FRAME is asserted. (The PCnet-PCI II controller
never performs more than one burst transaction within a
single bus mastership period). If EXTREQ is set to ONE,
the PCnet-PCI II controller does not deassert REQ until
it starts the last data phase of the transaction.
Once asserted, REQ remains active until GNT has be-
come active, independent of subsequent setting of the
STOP (CSR0, bit 2) or SPND (CSR5, bit 0). The asser-
tion of H_RESET or S_RESET, however, will cause
REQ to go inactive immediately.