AM79C970AKCW AMD [Advanced Micro Devices], AM79C970AKCW Datasheet - Page 160

• Manufacturer Part Number: AM79C970AKCW
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: AMD [Advanced Micro Devices]

Note that the PCnet-PCI II controller performs DWord
accesses to read the initialization block. This statement
is always true, regardless of the setting of the
SSIZE32 bit.
When SSIZE32 (BCR20, bit 8) is set to ONE, the soft-
ware structures are defined to be 32 bits wide. The base
address of the initialization block must be aligned to a
DWord boundary, i.e. CSR1, bits 1 and 0 must be
cleared to ZERO. When SSIZE32 is set to ONE, the
initialization block looks as shown in Table 37.
RLEN AND TLEN
When SSIZE32 (BCR20, bit 8) is set to ZERO, the soft-
ware structures are defined to be 16 bits wide, and the
RLEN and TLEN fields in the initialization block are each
3 bits wide. The values in these fields determine the
number of transmit and receive Descriptor Ring Entries
(DRE) which are used in the descriptor rings. Their
meaning is as follows:
160
IADR+0Ch
IADR+00h
IADR+04h
IADR+08h
IADR+10h
IADR+14h
IADR+18h
Address
IADR+0Ch
IADR+00h
IADR+02h
IADR+04h
IADR+06h
IADR+08h
IADR+0Ah
IADR+0Eh
IADR+10h
IADR+12h
IADR+14h
IADR+16h
Address
AMD
31–28
TLEN
Bits
Bits 15–13
RLEN
TLEN
27–24
RES
Bits
Table 36. Initialization Block (SSIZE32 = 0)
Table 37. Initialization Block (SSIZE32 = 1)
RES
Bit 12
23–20
RLEN
Bits
0
0
P R E L I M I N A R Y
Am79C970A
19–16
LADRF 15–00
LADRF 31–16
LADRF 47–32
LADRF 63–48
MODE 15–00
RES
RDRA 15–00
PADR 15–00
PADR 31–16
PADR 47–32
TDRA 15–00
Bits
Bits 11–8
PADR 31–00
RDRA 31–00
LADR 31–00
LADR 63–32
TDRA 31–00
RES
RES
If a value other than those listed in the above table is de-
sired, CSR76 and CSR78 can be written after initializa-
tion is complete.
When SSIZE32 (BCR20, bit 8) is set to ONE, the soft-
ware structures are defined to be 32 bits wide, and the
RLEN and TLEN fields in the initialization block are each
Table 38. R/TLEN Decoding (SSIZE32 = 0)
15–12
Bits
R/TLEN
000
001
010
011
100
101
110
111
Bits 7–4
11–8
Bits
PADR 47–32
RDRA 23–16
TDRA 23–16
MODE
Bits
7–4
No. of DREs
Bits 3–0
128
16
32
64
1
2
4
8
Bits
3–0