AM79C970AKCW AMD [Advanced Micro Devices], AM79C970AKCW Datasheet - Page 40

• Manufacturer Part Number: AM79C970AKCW
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: AMD [Advanced Micro Devices]

Parity Error Response
When the PCnet-PCI II controller is not the current bus
master, it samples the AD[31:0], C/BE[3:0] and the PAR
lines during the address phase of any PCI command for
a parity error. When it detects an address parity error,
the controller sets PERR (PCI Status register, bit 15) to
ONE. When reporting of that error is enabled by setting
SERREN (PCI Command register, bit 8) and PERREN
40
AMD
DEVSEL
FRAME
SERR
C/BE
PAR
Figure 10. Address Parity Error Response
CLK
AD
1
P R E L I M I N A R Y
Am79C970A
2
ADDR
CMD
(PCI Command register, bit 6) to ONE, the Pcnet-PCI II
controller also drives the SERR signal low for one clock
cycle and sets SERR (PCI Status register, bit 14) to
ONE. The assertion of SERR follows the address phase
by two clock cycles. The PCnet-PCI II controller will not
assert DEVSEL for a PCI transaction that has an ad-
dress parity error, when PERREN and SERREN are set
to ONE.
3
PAR
4
1st DATA
BE
PAR
5
19436A-13