MT48LC32M16A2P-75 L:C TR Micron Technology Inc, MT48LC32M16A2P-75 L:C TR Datasheet - Page 17

• Manufacturer Part Number: MT48LC32M16A2P-75 L:C TR
• Description: IC SDRAM 512MBIT 133MHZ 54TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT48LC32M16A2P-75 L:C TR

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-TSOP II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Commands
Table 6:
COMMAND INHIBIT
NO OPERATION (NOP)
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
Name (Function)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE
burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
Write enable/output enable
Write inhibit/output High-Z
Truth Table 1 – Commands and DQM Operation
Notes 1–2 apply to entire table; notes appear below
Notes:
Table 6 provides a quick reference of available commands. This is followed by a written
description of each command. Three additional Truth Tables appear in the Operations
section, beginning on page 35; these tables provide current state/next state information.
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0–A11 define the op-code written to the mode register, and A12 should be driven LOW.
3. A0–A12 provide row address, and BA0, BA1 determine which bank is made active.
4. A0–A9, A11, A12 (x4); A0–A9, A11 (x8); or A0–A9 (x16) provide column address; A10 HIGH
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged
6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock
The COMMAND INHIBIT function prevents new commands from being executed by the
SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively dese-
lected. Operations already in progress are not affected.
The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM that is
selected (CS# is LOW). This prevents unwanted commands from being registered during
idle or wait states. Operations already in progress are not affected.
enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto pre-
charge feature; BA0, BA1 determine which bank is being read from or written to.
and BA0, BA1 are “Don’t Care.”
for CKE.
delay).
CS#
H
L
L
L
L
L
L
L
L
–
–
17
RAS# CAS# WE#
X
H
H
H
H
L
L
L
L
–
–
Micron Technology, Inc., reserves the right to change products or specifications without notice.
X
H
H
H
H
L
L
L
L
–
–
X
H
H
H
H
L
L
L
L
–
–
512Mb: x4, x8, x16 SDRAM
DQM Address
L/H
L/H
H
X
X
X
X
X
X
X
L
8
8
Bank/row
Bank/col
Bank/col
Op-code
©2000 Micron Technology, Inc. All rights reserved.
Code
X
X
X
X
–
–
High-Z
Active
Active
Valid
Commands
DQs
X
X
X
X
X
X
X
Notes
6, 7
3
4
4
5
4
8
8