MT48LC32M16A2P-75 L:C TR Micron Technology Inc, MT48LC32M16A2P-75 L:C TR Datasheet - Page 38

• Manufacturer Part Number: MT48LC32M16A2P-75 L:C TR
• Description: IC SDRAM 512MBIT 133MHZ 54TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT48LC32M16A2P-75 L:C TR

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-TSOP II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 8:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
Row active
precharge
precharge
disabled)
disabled)
Current
State
Write
(auto
(auto
Read
Any
Idle
Truth Table 3 – Current State Bank n, Command to Bank n
Notes: 1–6 apply to entire table; notes appear below and on next page
CS#
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Notes:
RAS# CAS#
H
H
H
H
H
H
H
H
H
X
L
L
L
L
L
L
L
1. This table applies when CKE
2. This table is bank-specific, except where noted, that is, the current state is for a specific
3. Current state definitions:
4. The following states must not be interrupted by a command issued to the same bank. COM-
precharge enabled:
precharge enabled:
H
H
H
H
H
H
H
H
after
bank and the commands shown are those allowed to be issued to that bank when in that
state. Exceptions are covered in the notes below.
MAND INHIBIT or NOP commands or allowable commands to the other bank should be
issued on any clock edge occurring during these states. Allowable commands to the other
bank are determined by its current state and Table 8 and according to Table 9 on page 40.
X
L
L
L
L
L
L
L
L
Row activating: Starts with registration of an ACTIVE command and ends when
Read with auto
Write w/auto
Precharging: Starts with registration of a PRECHARGE command and ends when
t
WE#
XSR has been met (if the previous state was self refresh).
Row active: A row in the bank has been activated, and
X
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
Write: A WRITE burst has been initiated, with auto precharge disabled, and
Read: A READ burst has been initiated, with auto precharge disabled and has
COMMAND INHIBIT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
ACTIVE (Select and activate row)
AUTO REFRESH
LOAD MODE REGISTER
PRECHARGE
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Deactivate row in bank or banks)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Truncate READ burst, start PRECHARGE)
BURST TERMINATE
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE (Truncate WRITE burst, start PRECHARGE)
BURST TERMINATE
Idle: The bank has been precharged, and
is met. After
met. After
Starts with registration of a READ command with auto precharge
enabled and ends when
will be in the idle state.
Starts with registration of a WRITE command with auto precharge
enabled and ends when
will be in the idle state.
bursts/accesses and no register accesses are in progress.
not yet terminated or been terminated.
has not yet terminated or been terminated.
n - 1
38
t
RCD is met, the bank will be in the row active state.
was HIGH and CKE
t
RP is met, the bank will be in the idle state.
Command (Action)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
t
RP has been met. After
RP has been met. After
n
is HIGH (see Table 7 on page 37) and
512Mb: x4, x8, x16 SDRAM
t
RP has been met.
t
RCD has been met. No data
©2000 Micron Technology, Inc. All rights reserved.
t
t
RP is met, the bank
RP is met, the bank
Operations
Notes
t
RCD is
11
10
10
10
10
10
10
7
7
8
8
9
8
9
t
RP