MT48LC32M16A2P-75 L:C TR Micron Technology Inc, MT48LC32M16A2P-75 L:C TR Datasheet - Page 49

• Manufacturer Part Number: MT48LC32M16A2P-75 L:C TR
• Description: IC SDRAM 512MBIT 133MHZ 54TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT48LC32M16A2P-75 L:C TR

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-TSOP II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Timing Diagrams
Figure 33:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
DQML, DQMH
COMMAND
BA0, BA1
A11, A12
A0–A9,
DQM/
CKE
A10
DQ
CK
T = 100µs
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Power-up:
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CLK stable
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MIN
DD
Initialize and Load Mode Register
and
t CKS
t CMS
Notes:
T0
NOP
t CKH
High-Z
t CMH
SINGLE BANK
t CMS
ALL BANKS
t CK
1. If CS is HIGH at clock high time, all commands applied are NOP.
2. The mode register may be loaded prior to the AUTO REFRESH cycles if desired.
3. JEDEC and PC100 specify three clocks.
4. Outputs are guaranteed High-Z after command is issued.
5. A12 should be a LOW at Tp + 1.
PRECHARGE
BANKS
T1
ALL
t CMH
t RP
Precharge
all banks
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t CMS
Tn + 1
REFRESH
AUTO
t CMH
t CH
AUTO REFRESH
t RFC
NOP
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NOP
49
t CL
To + 1
REFRESH
AUTO
AUTO REFRESH
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t RFC
NOP
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NOP
512Mb: x4, x8, x16 SDRAM
t AS
t AS
LOAD MODE
Tp + 1
REGISTER
CODE
CODE
t AH
t AH
Program mode register
5
©2000 Micron Technology, Inc. All rights reserved.
t MRD
Timing Diagrams
Tp + 2
NOP
2, 3, 4
Tp + 3
ACTIVE
BANK
ROW
ROW
Don’t Care