MT48LC32M16A2P-75 L:C TR Micron Technology Inc, MT48LC32M16A2P-75 L:C TR Datasheet - Page 40

• Manufacturer Part Number: MT48LC32M16A2P-75 L:C TR
• Description: IC SDRAM 512MBIT 133MHZ 54TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT48LC32M16A2P-75 L:C TR

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-TSOP II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 9:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
Current State
precharging
precharge)
precharge)
activating,
(with auto
(with auto
precharge
precharge
active, or
disabled)
disabled)
Write
Write
(auto
(auto
Read
Read
Row
Any
Idle
Truth Table 4 – Current State Bank n, Command to Bank m
Notes 1–6 apply to entire table; notes appear below and on next page
CS#
Notes:
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS#
1. This table applies when CKE
2. This table describes alternate bank operation, except where noted; that is, the current state
3. Current state definitions:
4. AUTO REFRESH, SELF REFRESH, and LOAD MODE REGISTER commands may only be issued
X
H
X
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
precharge enabled:
precharge enabled:
after
is for bank n and the commands shown are those allowed to be issued to bank m (assuming
that bank m is in such a state that the given command is allowable). Exceptions are covered
in the notes below.
when all banks are idle.
Write with auto
Read with auto
CAS#
t
XSR has been met (if the previous state was self refresh).
X
H
X
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
Row active: A row in the bank has been activated, and
Write: A WRITE burst has been initiated, with auto precharge disabled, and
Read: A READ burst has been initiated, with auto precharge disabled, and has
Idle: The bank has been precharged, and
WE#
H
H
H
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
L
L
L
L
bursts/accesses and no register accesses are in progress.
not yet terminated or been terminated.
has not yet terminated or been terminated.
Starts with registration of a READ command with auto precharge
enabled, and ends when
will be in the idle state.
Starts with registration of a WRITE command with auto precharge
enabled, and ends when
will be in the idle state.
Command (Action)
COMMAND INHIBIT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
Any command otherwise allowed to bank m
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
n - 1
40
was HIGH and CKE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
t
RP has been met. After
RP has been met. After
n
is HIGH (see Table 7 on page 37) and
512Mb: x4, x8, x16 SDRAM
t
RP has been met.
t
RCD has been met. No data
©2000 Micron Technology, Inc. All rights reserved.
t
t
RP is met, the bank
RP is met, the bank
Operations
7, 8, 14
7, 8, 15
7, 8, 16
7, 8, 17
Notes
7, 10
7, 11
7, 12
7, 13
7
7
9
9
9
9