MT48LC32M16A2P-75 L:C TR Micron Technology Inc, MT48LC32M16A2P-75 L:C TR Datasheet - Page 18

• Manufacturer Part Number: MT48LC32M16A2P-75 L:C TR
• Description: IC SDRAM 512MBIT 133MHZ 54TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT48LC32M16A2P-75 L:C TR

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-TSOP II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LOAD MODE REGISTER
ACTIVE
READ
WRITE
PRECHARGE
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
The mode register is loaded via inputs A0–A11 (A12 should be driven LOW). See “Mode
Register” on page 13. The LOAD MODE REGISTER command can only be issued when
all banks are idle, and a subsequent executable command cannot be issued until
is met.
The ACTIVE command is used to open (or activate) a row in a particular bank for a
subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address
provided on inputs A0–A12 selects the row. This row remains active (or open) for
accesses until a PRECHARGE command is issued to that bank. A PRECHARGE
command must be issued before opening a different row in the same bank.
The READ command is used to initiate a burst read access to an active row. The value on
the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A9, A11,
A12 (x4); A0–A9, A11 (x8); or A0–A9 (x16) selects the starting column location. The value
on input A10 determines whether auto precharge is used. If auto precharge is selected,
the row being accessed will be precharged at the end of the READ burst; if auto
precharge is not selected, the row will remain open for subsequent accesses. Read data
appears on the DQs subject to the logic level on the DQM inputs two clocks earlier. If a
given DQM signal was registered HIGH, the corresponding DQs will be High-Z two
clocks later; if the DQM signal was registered LOW, the DQs will provide valid data.
The WRITE command is used to initiate a burst write access to an active row. The value
on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A9, A11,
A12 (x4); A0–A9, A11 (x8); or A0–A9 (x16) selects the starting column location. The value
on input A10 determines whether auto precharge is used. If auto precharge is selected,
the row being accessed will be precharged at the end of the WRITE burst; if auto
precharge is not selected, the row will remain open for subsequent accesses. Input data
appearing on the DQs is written to the memory array subject to the DQM input logic
level appearing coincident with the data. If a given DQM signal is registered LOW, the
corresponding data will be written to memory; if the DQM signal is registered HIGH, the
corresponding data inputs will be ignored, and a WRITE will not be executed to that
byte/column location.
The PRECHARGE command is used to deactivate the open row in a particular bank or
the open row in all banks. The bank(s) will be available for a subsequent row access a
specified time (
whether one or all banks are to be precharged, and in the case where only one bank is to
be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as
“Don’t Care.” After a bank has been precharged, it is in the idle state and must be acti-
vated prior to any READ or WRITE commands being issued to that bank.
t
RP) after the PRECHARGE command is issued. Input A10 determines
18
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512Mb: x4, x8, x16 SDRAM
©2000 Micron Technology, Inc. All rights reserved.
Commands
t
MRD