MT48LC32M16A2P-75 L:C TR Micron Technology Inc, MT48LC32M16A2P-75 L:C TR Datasheet - Page 19

• Manufacturer Part Number: MT48LC32M16A2P-75 L:C TR
• Description: IC SDRAM 512MBIT 133MHZ 54TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT48LC32M16A2P-75 L:C TR

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-TSOP II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Auto Precharge
BURST TERMINATE
AUTO REFRESH
SELF REFRESH
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
Auto precharge is a feature that performs the same individual-bank PRECHARGE func-
tion described above, without requiring an explicit command. This is accomplished by
using A10 to enable auto precharge in conjunction with a specific READ or WRITE
command. A PRECHARGE of the bank/row that is addressed with the READ or WRITE
command is automatically performed upon completion of the READ or WRITE burst,
except in the full-page burst mode, where auto precharge does not apply. Auto precharge
is nonpersistent in that it is either enabled or disabled for each individual READ or
WRITE command.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a
burst. The user must not issue another command to the same bank until the precharge
time (
issued at the earliest possible time, as described for each burst type in the “Operations”
section on page 20.
The BURST TERMINATE command is used to truncate either fixed-length or full-page
bursts. The most recently registered READ or WRITE command prior to the BURST
TERMINATE command will be truncated, as shown in the “Operations” section on
page 20. The BURST TERMINATE command does not precharge the row; the row will
remain open until a PRECHARGE command is issued.
AUTO REFRESH is used during normal operation of the SDRAM and is analogous to
CAS#-BEFORE-RAS# (CBR) REFRESH in conventional DRAMs. This command is
nonpersistent, so it must be issued each time a refresh is required. All active banks must
be PRECHARGED prior to issuing an AUTO REFRESH command. The AUTO REFRESH
command should not be issued until the minimum
PRECHARGE command as shown in the “Operations” section on page 20.
The addressing is generated by the internal refresh controller. This makes the address
bits “Don’t Care” during an AUTO REFRESH command. The 512Mb SDRAM requires
8,192 AUTO REFRESH cycles every 64ms (
distributed AUTO REFRESH command every 7.81µs will meet the refresh requirement
and ensure that each row is refreshed. Alternatively, 8,192 AUTO REFRESH commands
can be issued in a burst at the minimum cycle rate (
The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest
of the system is powered down. When in the self refresh mode, the SDRAM retains data
without external clocking. The SELF REFRESH command is initiated like an AUTO
REFRESH command except CKE is disabled (LOW). After the SELF REFRESH command
is registered, all the inputs to the SDRAM become “Don’t Care” with the exception of
CKE, which must remain LOW.
After self refresh mode is engaged, the SDRAM provides its own internal clocking,
causing it to perform its own AUTO REFRESH cycles. The SDRAM must remain in self
refresh mode for a minimum period equal to
for an indefinite period beyond that.
t
RP) is completed. This is determined as if an explicit PRECHARGE command was
19
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
REF), regardless of width option. Providing a
t
RAS and may remain in self refresh mode
t
t
RC), once every 64ms.
RP has been met after the
512Mb: x4, x8, x16 SDRAM
©2000 Micron Technology, Inc. All rights reserved.
Commands