MT48LC32M16A2P-75 L:C TR Micron Technology Inc, MT48LC32M16A2P-75 L:C TR Datasheet - Page 50

IC SDRAM 512MBIT 133MHZ 54TSOP

MT48LC32M16A2P-75 L:C TR

Manufacturer Part Number
MT48LC32M16A2P-75 L:C TR
Description
IC SDRAM 512MBIT 133MHZ 54TSOP
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT48LC32M16A2P-75 L:C TR

Format - Memory
RAM
Memory Type
SDRAM
Memory Size
512M (32Mx16)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
54-TSOP II
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 34:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
DQML, DQMU
Power-Down Mode
COMMAND
Precharge all
BA0, BA1
A11, A12
active banks
A0–A9,
DQM/
CKE
CLK
A10
DQ
Note:
t CMS
High-Z
t CKS
t AS
SINGLE BANK
PRECHARGE
ALL BANKS
BANK(S)
T0
t CMH
t CKH
t AH
Violating refresh requirements during power-down may result in a loss of data.
Two clock cycles
All banks idle, enter
power-down mode
t CK
T1
NOP
t CKS
t CL
T2
NOP
Input buffers gated off while in
power-down mode
t CH
50
Exit power-down mode
(
(
(
(
(
(
(
)
(
)
(
)
(
)
(
)
)
(
)
)
)
(
)
)
(
)
(
(
(
(
(
(
)
)
(
)
(
)
(
)
(
)
(
)
)
(
)
)
)
)
)
(
)
(
)
)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
(
(
(
(
(
(
)
(
)
(
)
(
(
(
(
)
(
)
)
)
)
)
)
)
(
)
)
(
(
(
)
(
(
(
)
(
)
(
)
(
(
(
(
)
(
)
)
)
)
)
(
)
)
)
)
)
t CKS
Tn + 1
512Mb: x4, x8, x16 SDRAM
NOP
All banks idle
©2000 Micron Technology, Inc. All rights reserved.
Tn + 2
ACTIVE
ROW
ROW
BANK
Timing Diagrams
Don’t Care

Related parts for MT48LC32M16A2P-75 L:C TR