MT48LC32M16A2P-75 L:C TR Micron Technology Inc, MT48LC32M16A2P-75 L:C TR Datasheet - Page 28

• Manufacturer Part Number: MT48LC32M16A2P-75 L:C TR
• Description: IC SDRAM 512MBIT 133MHZ 54TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT48LC32M16A2P-75 L:C TR

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-TSOP II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WRITEs
Figure 17:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
WRITE Command
WRITE bursts are initiated with a WRITE command, as shown in Figure 17.
The starting column and bank addresses are provided with the WRITE command, and
auto precharge is either enabled or disabled for that access. If auto precharge is enabled,
the row being accessed is precharged at the completion of the burst. For the generic
WRITE commands used in the following illustrations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element will be registered coincident with
the WRITE command. Subsequent data elements will be registered on each successive
positive clock edge. Upon completion of a fixed-length burst, assuming no other
commands have been initiated, the DQs will remain High-Z and any additional input
data will be ignored (see Figure 18 on page 29). A full-page burst will continue until
terminated (at the end of the page, it will wrap to the start address and continue). Data
for any WRITE burst may be truncated with a subsequent WRITE command, and data
for a fixed-length WRITE burst may be immediately followed by data for a WRITE
command. The new WRITE command can be issued on any clock following the previous
WRITE command, and the data provided coincident with the new command applies to
the new command. An example is shown in Figure 19 on page 29. Data n + 1 is either the
last of a burst of two or the last desired of a longer burst. The 512Mb SDRAM uses a pipe-
lined architecture and therefore does not require the 2n rule associated with a prefetch
architecture. A WRITE command can be initiated on any clock cycle following a previous
WRITE command. Full-speed random write accesses within a page can be performed to
the same bank, as shown in Figure 20 on page 30, or each subsequent WRITE may be
performed to a different bank.
A0–A9, A11, A12: x4
A0–A9, A11: x8
A11, A12: x16
A0–A9: x16
BA0, BA1
A12: x8
CAS#
RAS#
WE#
A10
CKE
CLK
CS#
HIGH
DISABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
28
COLUMN
ADDRESS
ADDRESS
BANK
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Don’t Care
512Mb: x4, x8, x16 SDRAM
©2000 Micron Technology, Inc. All rights reserved.
Operations