MA180023 Microchip Technology, MA180023 Datasheet - Page 334

• Manufacturer Part Number: MA180023
• Description: MODULE PLUG-IN PIC18F46J11 PIM
• Manufacturer: Microchip Technology
• Series: PIC®r

Specifications of MA180023

• Accessory Type: Plug-In Module (PIM) - PIC18F46J11
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: PIC18
• Supported Devices: Stand-alone Or W/ HPC(DM183022) Or PIC18(DM183032)
• Silicon Manufacturer: Microchip
• Core Architecture: PIC
• Core Sub-architecture: PIC18
• Silicon Core Number: PIC18F
• Silicon Family Name: PIC18FxxJxx
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: HPC Explorer Board (DM183022) or PIC18 Explorer Board (DM183032)
• For Use With: DM183032 - BOARD EXPLORER PICDEM PIC18DM183022 - BOARD DEMO PIC18FXX22 64/80TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F46J11 FAMILY
FIGURE 19-7:
TABLE 19-6:
19.2.4
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the BRG is inactive and a
proper byte reception cannot be performed. The
auto-wake-up feature allows the controller to wake-up
due to activity on the RXx/DTx line while the EUSART
is operating in Asynchronous mode.
The auto-wake-up feature is enabled by setting the
WUE bit (BAUDCONx<1>). Once set, the typical
receive sequence on RXx/DTx is disabled and the
DS39932C-page 334
INTCON
PIR1
PIE1
IPR1
PIR3
PIE3
IPR3
RCSTAx
RCREGx
TXSTAx
BAUDCONx ABDOVF
SPBRGHx
SPBRGx
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1:
Name
Note: This timing diagram shows three words appearing on the RXx input. The RCREGx (Receive Buffer) is read after
RXx (pin)
Rcv Shift Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREGx
RCxIF
(Interrupt Flag)
OERR bit
CREN
the third word causing the OERR (Overrun) bit to be set.
These bits are only available on 44-pin devices.
AUTO-WAKE-UP ON SYNC BREAK
CHARACTER
EUSARTx Receive Register
EUSARTx Baud Rate Generator Register High Byte
EUSARTx Baud Rate Generator Register Low Byte
GIE/GIEH PEIE/GIEL TMR0IE
PMPIE
PMPIP
PMPIF
SSP2IF
SSP2IE
SSP2IP
CSRC
SPEN
Bit 7
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
(1)
(1)
(1)
ASYNCHRONOUS RECEPTION
Start
bit
BCL2IE
BCL2IP
BCL2IF
bit 0
RCIDL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
bit 1
RXDTP
RC1IE
RC1IP
RC2IE
RC2IP
RC1IF
RC2IF
SREN
TXEN
Bit 5
bit 7/8
TXCKP
Stop
INT0IE
TX1IF
TX1IE
TX1IP
TX2IF
TX2IE
TX2IP
CREN
SYNC
bit
Bit 4
Word 1
RCREGx
Start
bit
TMR4IE
TMR4IP
TMR4IF
SSP1IF
SSP1IE
SSP1IP
ADDEN
SENDB
BRG16
bit 0
EUSART remains in an Idle state, monitoring for a
wake-up event independent of the CPU mode. A
wake-up event consists of a high-to-low transition on
the RXx/DTx line. (This coincides with the start of a
Sync Break or a Wake-up Signal character for the LIN
protocol.)
Following a wake-up event, the module generates an
RCxIF interrupt. The interrupt is generated synchro-
nously to the Q clocks in normal operating modes
(Figure 19-8) and asynchronously if the device is in
Sleep mode (Figure 19-9). The interrupt condition is
cleared by reading the RCREGx register.
RBIE
Bit 3
CTMUIE TMR3GIE
CTMUIP TMR3GIP
CTMUIF TMR3GIF
TMR0IF
CCP1IF
CCP1IE
CCP1IP
bit 7/8
BRGH
FERR
Word 2
RCREGx
Bit 2
—
Stop
bit
TMR2IF
TMR2IE
TMR2IP
INT0IF
OERR
TRMT
WUE
Start
Bit 1
© 2009 Microchip Technology Inc.
bit
TMR1IF
TMR1IE
TMR1IP
RTCCIE
RTCCIP
RTCCIF
ABDEN
RX9D
TX9D
RBIF
Bit 0
bit 7/8
Stop
bit
on Page:
Values
Reset
63
65
65
65
65
65
65
65
65
65
66
66
65