C8051F326DK Silicon Laboratories Inc, C8051F326DK Datasheet - Page 58

• Manufacturer Part Number: C8051F326DK
• Description: KIT DEV FOR C8051F326/7
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F326DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F326/F327
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F326
• Silicon Family Name: C8051F32x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F326, C8051F327
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1306

C8051F326/7
7.1.
During power-up, the device is held in a reset state and the RST pin is driven low until VDD settles above
V
typically less than 0.3 ms. Figure 7.2. plots the power-on and VDD monitor reset timing.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000) software can
read the PORSF flag to determine if a power-up was the cause of reset. The content of internal data mem-
ory should be assumed to be undefined after a power-on reset. The VDD monitor is enabled following a
power-on reset.
Software can force a power-on reset by writing ‘1’ to the PINRSF bit in register RSTSRC.
58
RST
. A Power-On Reset delay (T
Logic HIGH
Logic LOW
Power-On Reset
2.70
2.4
2.0
1.0
Figure 7.2. Power-On and VDD Monitor Reset Timing
/RST
V
RST
Power-On
PORDelay
Reset
T
PORDelay
) occurs before the device is released from reset; this delay is
Rev. 1.1
Monitor
Reset
VDD
VDD
t