C8051F560-TB Silicon Laboratories Inc, C8051F560-TB Datasheet - Page 118
![BOARD PROTOTYPE W/C8051F560](/photos/9/25/92557/c8051f560-tb_sml.jpg)
C8051F560-TB
Manufacturer Part Number
C8051F560-TB
Description
BOARD PROTOTYPE W/C8051F560
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.TOOLSTICK560DC.pdf
(302 pages)
Specifications of C8051F560-TB
Contents
Board
Processor To Be Evaluated
C8051F56x
Processor Series
C8051F56x
Interface Type
USB
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
1.8 V to 5.25 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F55x, C8051F56x, C8051F57x
For Use With
336-1691 - KIT DEVELOPMENT FOR C8051F560
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1694
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C8051F55x/56x/57x
SFR Definition 13.3. EIE1: Extended Interrupt Enable 1
SFR Address = 0xE6; SFR Page = All Pages
118
Name
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
EWADC0 Enable Window Comparison ADC0 Interrupt.
EADC0
ESMB0
EPCA0
Name
ELIN0
ECP1
ECP0
ET3
ELIN0
R/W
7
0
Enable LIN0 Interrupt.
This bit sets the masking of the LIN0 interrupt.
0: Disable LIN0 interrupts.
1: Enable interrupt requests generated by the LIN0INT flag.
Enable Timer 3 Interrupt.
This bit sets the masking of the Timer 3 interrupt.
0: Disable Timer 3 interrupts.
1: Enable interrupt requests generated by the TF3L or TF3H flags.
Enable Comparator1 (CP1) Interrupt.
This bit sets the masking of the CP1 interrupt.
0: Disable CP1 interrupts.
1: Enable interrupt requests generated by the CP1RIF or CP1FIF flags.
Enable Comparator0 (CP0) Interrupt.
This bit sets the masking of the CP0 interrupt.
0: Disable CP0 interrupts.
1: Enable interrupt requests generated by the CP0RIF or CP0FIF flags.
Enable Programmable Counter Array (PCA0) Interrupt.
This bit sets the masking of the PCA0 interrupts.
0: Disable all PCA0 interrupts.
1: Enable interrupt requests generated by PCA0.
Enable ADC0 Conversion Complete Interrupt.
This bit sets the masking of the ADC0 Conversion Complete interrupt.
0: Disable ADC0 Conversion Complete interrupt.
1: Enable interrupt requests generated by the AD0INT flag.
This bit sets the masking of ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison interrupt.
1: Enable interrupt requests generated by ADC0 Window Compare flag (AD0WINT).
Enable SMBus (SMB0) Interrupt.
This bit sets the masking of the SMB0 interrupt.
0: Disable all SMB0 interrupts.
1: Enable interrupt requests generated by SMB0.
R/W
ET3
6
0
ECP1
R/W
5
0
ECP0
R/W
Rev. 1.1
4
0
Function
EPCA0
R/W
3
0
EADC0
R/W
2
0
EWADC0
R/W
1
0
ESMB0
R/W
0
0
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