C8051F560-TB Silicon Laboratories Inc, C8051F560-TB Datasheet - Page 187
C8051F560-TB
Manufacturer Part Number
C8051F560-TB
Description
BOARD PROTOTYPE W/C8051F560
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.TOOLSTICK560DC.pdf
(302 pages)
Specifications of C8051F560-TB
Contents
Board
Processor To Be Evaluated
C8051F56x
Processor Series
C8051F56x
Interface Type
USB
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
1.8 V to 5.25 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F55x, C8051F56x, C8051F57x
For Use With
336-1691 - KIT DEVELOPMENT FOR C8051F560
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1694
- Current page: 187 of 302
- Download datasheet (3Mb)
SFR Definition 19.23. P2SKIP: Port 2 Skip
SFR Address = 0xD6; SFR Page = 0x0F
SFR Definition 19.24. P3: Port 3
SFR Address = 0xB0; SFR Page = All Pages; Bit-Addressable
Note: P2.2-P2.7 are available on 40-pin and 32-pin packages.
Note: P3.0 is available on 40-pin and 32-pin packages. P3.1-P3.7 are available on 40-pin packages
Name
Reset
Name
Reset
Bit
7:0
Bit
7:0
Type
Type
Bit
Bit
P2SKIP[7:0]
P3[7:0]
Name
Name
7
0
7
1
Port 3 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
Port 2 Crossbar Skip Enable Bits.
These bits select Port 2 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P2.n pin is not skipped by the Crossbar.
1: Corresponding P2.n pin is skipped by the Crossbar.
6
0
6
1
Description
5
0
5
1
Rev. 1.1
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
4
0
4
1
P2SKIP[7:0]
P3[7:0]
R/W
R/W
Function
Write
3
0
3
1
C8051F55x/56x/57x
2
0
2
1
0: P3.n Port pin is logic
LOW.
1: P3.n Port pin is logic
HIGH.
1
0
1
1
Read
0
0
0
1
187
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