C8051F560-TB Silicon Laboratories Inc, C8051F560-TB Datasheet - Page 196
![BOARD PROTOTYPE W/C8051F560](/photos/9/25/92557/c8051f560-tb_sml.jpg)
C8051F560-TB
Manufacturer Part Number
C8051F560-TB
Description
BOARD PROTOTYPE W/C8051F560
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.TOOLSTICK560DC.pdf
(302 pages)
Specifications of C8051F560-TB
Contents
Board
Processor To Be Evaluated
C8051F56x
Processor Series
C8051F56x
Interface Type
USB
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
1.8 V to 5.25 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F55x, C8051F56x, C8051F57x
For Use With
336-1691 - KIT DEVELOPMENT FOR C8051F560
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1694
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- Download datasheet (3Mb)
C8051F55x/56x/57x
The application should perform the following steps when an interrupt is requested.
1. Check the DONE bit (LIN0ST.0) and the ERROR bit (LIN0ST.2).
2. If performing a master receive operation and the transfer was successful, read the received data from
3. If the transfer was not successful, check the error register to determine the kind of error. Further error
4. Set the RSTINT (LIN0CTRL.3) and RSTERR bits (LIN0CTRL.2) to reset the interrupt request and the
20.4. LIN Slave Mode Operation
When the device is configured for slave mode operation, it must wait for a command from a master node.
Access from the firmware to the data buffer and ID registers of the LIN controller is only possible when a
data request is pending (DTREQ bit (LIN0ST.4) is 1) and also when the LIN bus is not active (ACTIVE bit
(LIN0ST.7) is set to 0).
The LIN controller in slave mode detects the header of the message frame sent by the LIN master. If slave
synchronization is enabled (autobaud), the slave synchronizes its internal bit time to the master bit time.
The LIN controller configured for slave mode will generated an interrupt in one of three situations:
1. After the reception of the IDENTIFIER FIELD
2. When an error is detected
3. When the message transfer is completed.
The application should perform the following steps when an interrupt is detected:
1. Check the status of the DTREQ bit (LIN0ST.4). This bit is set when the IDENTIFIER FIELD has been
2. If DTREQ (LIN0ST.4) is set, read the identifier from LIN0ID and process it. If DTREQ (LIN0ST.4) is not
3. Set the TXRX bit (LIN0CTRL.5) to 1 if the current frame is a transmit operation for the slave and set to
4. Load the data length into LIN0SIZE.
5. For a slave transmit operation, load the data to transmit into the data buffer.
6. Set the DTACK bit (LIN0CTRL.4). Continue to step 10.
7. If DTREQ (LIN0ST.4) is not set, check the DONE bit (LIN0ST.0). The transmission was successful if the
8. If the transmission was successful and the current frame was a receive operation for the slave, load the
9. If the transmission was not successful, check LIN0ERR to determine the nature of the error. Further
10.Set the RSTINT (LIN0CTRL.3) and RSTERR bits (LIN0CTRL.2) to reset the interrupt request and the
In addition to these steps, the application should be aware of the following:
1. If the current frame is a transmit operation for the slave, steps 1 through 5 must be completed during
2. If the current frame is a receive operation for the slave, steps 1 through 5 have to be finished until the
196
the data buffer.
handling has to be done by the application.
error flags.
received.
set, continue to step 7.
0 if the current frame is a receive operation for the slave.
DONE bit is set.
received data bytes from the data buffer.
error handling has to be done by the application.
error flags.
the IN-FRAME RESPONSE SPACE. If it is not completed in time, a timeout will be detected by the
master.
reception of the first byte after the IDENTIFIER FIELD. Otherwise, the internal receive buffer of the LIN
controller will be overwritten and a timeout error will be detected in the LIN controller.
Rev. 1.1
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