C8051F560-TB Silicon Laboratories Inc, C8051F560-TB Datasheet - Page 98
![BOARD PROTOTYPE W/C8051F560](/photos/9/25/92557/c8051f560-tb_sml.jpg)
C8051F560-TB
Manufacturer Part Number
C8051F560-TB
Description
BOARD PROTOTYPE W/C8051F560
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.TOOLSTICK560DC.pdf
(302 pages)
Specifications of C8051F560-TB
Contents
Board
Processor To Be Evaluated
C8051F56x
Processor Series
C8051F56x
Interface Type
USB
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
1.8 V to 5.25 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F55x, C8051F56x, C8051F57x
For Use With
336-1691 - KIT DEVELOPMENT FOR C8051F560
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1694
- Current page: 98 of 302
- Download datasheet (3Mb)
C8051F55x/56x/57x
While CIP-51 executes in-line code (writing values to SPI0DAT in this example), the CAN0 Interrupt
occurs. The CIP-51 vectors to the CAN0 ISR and pushes the current SFR Page value (SFR Page 0x00)
into SFRNEXT in the SFR Page Stack. The SFR page needed to access CAN’s SFRs is then automatically
placed in the SFRPAGE register (SFR Page 0x0C). SFRPAGE is considered the “top” of the SFR Page
Stack. Software can now access the CAN0 SFRs. Software may switch to any SFR Page by writing a new
value to the SFRPAGE register at any time during the CAN0 ISR to access SFRs that are not on SFR
Page 0x0C. See Figure 12.3.
SFR Page 0xC
Automatically
pushed on stack in
SFRPAGE on CAN0
interrupt
0xC
SFRPAGE
(CAN0)
SFRPAGE
pushed to
0x0
SFRNEXT
SFRNEXT
(SPI0DAT)
SFRLAST
Figure 12.3. SFR Page Stack After CAN0 Interrupt Occurs
98
Rev. 1.1
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