C8051F560-TB Silicon Laboratories Inc, C8051F560-TB Datasheet - Page 239
![BOARD PROTOTYPE W/C8051F560](/photos/9/25/92557/c8051f560-tb_sml.jpg)
C8051F560-TB
Manufacturer Part Number
C8051F560-TB
Description
BOARD PROTOTYPE W/C8051F560
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.TOOLSTICK560DC.pdf
(302 pages)
Specifications of C8051F560-TB
Contents
Board
Processor To Be Evaluated
C8051F56x
Processor Series
C8051F56x
Interface Type
USB
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
1.8 V to 5.25 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F55x, C8051F56x, C8051F57x
For Use With
336-1691 - KIT DEVELOPMENT FOR C8051F560
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1694
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SFR Definition 23.2. SMOD0: Serial Port 0 Control
SFR Address = 0xA9; SFR Page = 0x00
Name
Reset
Bit
6:5 S0PT[1:0] Parity Type Select Bits.
3:2 S0DL[1:0] Data Length.
Type
7
4
1
0
Bit
MCE0
Name
XBE0
SBL0
PE0
MCE0
R/W
7
0
Multiprocessor Communication Enable.
0: RI0 will be activated if stop bit(s) are 1.
1: RI0 will be activated if stop bit(s) and extra bit are 1. Extra bit must be enabled using
XBE0.
00: Odd Parity
01: Even Parity
10: Mark Parity
11: Space Parity.
Parity Enable.
This bit enables hardware parity generation and checking. The parity type is selected
by bits S0PT[1:0] when parity is enabled.
0: Hardware parity is disabled.
1: Hardware parity is enabled.
00: 5-bit data
01: 6-bit data
10: 7-bit data
11: 8-bit data
Extra Bit Enable.
When enabled, the value of TBX0 will be appended to the data field
0: Extra Bit is disabled.
1: Extra Bit is enabled.
Stop Bit Length.
0: Short—stop bit is active for one bit time
1: Long—stop bit is active for two bit times (data length = 6, 7, or 8 bits), or 1.5 bit times
(data length = 5 bits).
R/W
6
0
S0PT[1:0]
R
5
0
PE0
R/W
Rev. 1.1
4
0
Function
R/W
3
1
S0DL[1:0]
C8051F55x/56x/57x
R/W
2
1
XBE0
R/W
1
0
SBL0
R/W
0
0
239
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