C8051F560-TB Silicon Laboratories Inc, C8051F560-TB Datasheet - Page 179
![BOARD PROTOTYPE W/C8051F560](/photos/9/25/92557/c8051f560-tb_sml.jpg)
C8051F560-TB
Manufacturer Part Number
C8051F560-TB
Description
BOARD PROTOTYPE W/C8051F560
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.TOOLSTICK560DC.pdf
(302 pages)
Specifications of C8051F560-TB
Contents
Board
Processor To Be Evaluated
C8051F56x
Processor Series
C8051F56x
Interface Type
USB
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
1.8 V to 5.25 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F55x, C8051F56x, C8051F57x
For Use With
336-1691 - KIT DEVELOPMENT FOR C8051F560
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1694
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SFR Definition 19.8. P2MASK: Port 2 Mask Register
SFR Address = 0xB2; SFR Page = 0x00
SFR Definition 19.9. P2MAT: Port 2 Match Register
SFR Address = 0xB1; SFR Page = 0x00
Note: P2.2–P2.7 are available on 40-pin and 32-pin packages.
Note: P2.2–P2.7 are available on 40-pin and 32-pin packages.
Name
Reset
Name
Reset
Bit
7:0
Bit
7:0
Type
Type
Bit
Bit
P2MASK[7:0]
P2MAT[7:0]
Name
Name
7
0
7
1
Port 2 Mask Value.
Selects P2 pins to be compared to the corresponding bits in P2MAT.
0: P2.n pin logic value is ignored and cannot cause a Port Mismatch event.
1: P2.n pin logic value is compared to P2MAT.n.
Port 2 Match Value.
Match comparison value used on Port 2 for bits in P2MAT which are set to 1.
0: P2.n pin logic value is compared with logic LOW.
1: P2.n pin logic value is compared with logic HIGH.
6
0
6
1
5
0
5
1
Rev. 1.1
P2MASK[7:0]
4
0
4
1
P2MAT[7:0]
R/W
R/W
Function
Function
3
0
3
1
C8051F55x/56x/57x
2
0
2
1
1
0
1
1
0
0
0
1
179
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