C8051F560-TB Silicon Laboratories Inc, C8051F560-TB Datasheet - Page 31
C8051F560-TB
Manufacturer Part Number
C8051F560-TB
Description
BOARD PROTOTYPE W/C8051F560
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.TOOLSTICK560DC.pdf
(302 pages)
Specifications of C8051F560-TB
Contents
Board
Processor To Be Evaluated
C8051F56x
Processor Series
C8051F56x
Interface Type
USB
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
1.8 V to 5.25 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F55x, C8051F56x, C8051F57x
For Use With
336-1691 - KIT DEVELOPMENT FOR C8051F560
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1694
- Current page: 31 of 302
- Download datasheet (3Mb)
Notes:
General
Solder Mask Design
Stencil Design
Card Assembly
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
7. A No-Clean, Type-3 solder paste is recommended.
8. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Dimension
metal pad is to be 60 m minimum, all the way around the pad.
good solder paste release.
Components.
C1
C2
E
Table 4.4. QFP-32 Landing Diagram Dimensions
8.40
8.40
Min
Figure 4.4. QFP-32 Landing Diagram
0.80 BSC
Max
8.50
8.50
Rev. 1.1
Dimension
X1
Y1
C8051F55x/56x/57x
0.40
1.25
Min
Max
0.50
1.35
31
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