IPR-NIOS Altera, IPR-NIOS Datasheet - Page 111

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 4: Instantiating the Nios II Processor in SOPC Builder
Core Nios II Page
December 2010 Altera Corporation
Multiply and Divide Settings
Reset Vector
f
f
■
As shown in
lists the basic properties of each core.
For complete details of each core, refer to the
chapter of the Nios II Processor Reference Handbook.
The Nios II/s and Nios II/f cores offer hardware multiply and divide options. You
can choose the best option to balance embedded multiplier usage, logic element (LE)
usage, and performance.
The Hardware Multiply setting for each core provides a subset of the options in the
following list:
■
■
■
■
Turning on Hardware Divide includes LE-based divide hardware in the ALU. The
Hardware Divide option achieves much greater performance than software
emulation of divide operations.
For details on the performance effects of the Hardware Multiply and Hardware
Divide options, refer to the
Processor Reference Handbook.
You can select the memory module where the reset code (boot loader) resides, and the
location of the reset vector (reset address). The reset vector cannot be configured until
your system memory components are in place.
The Memory list, which includes all memory modules mastered by the Nios II
processor, allows you to select the reset vector memory module. In a typical system,
you select a nonvolatile memory module for the reset code.
Offset allows you to specify the location of the reset vector relative to the memory
module’s base address. SOPC Builder calculates the physical address of the reset
vector when you modify the memory module, the offset, or the memory module’s
base address, and displays the address next to the Offset box. This address, displayed
next to the Offset box, is always a physical address, even when an MMU is present.
Nios II/e—The Nios II/e “economy” core is designed to achieve the smallest
possible core size. As a result, this core has a limited feature set, and many settings
are not available when the Nios II/e core is selected.
DSP Block—Include DSP block multipliers in the arithmetic logic unit (ALU).
This option is only present when targeting devices that have DSP block
multipliers.
Embedded Multipliers—Include embedded multipliers in the ALU. This option is
only present when targeting FPGA devices that have embedded multipliers.
Logic Elements—Include LE-based multipliers in the ALU. This option achieves
high multiply performance without consuming embedded multiplier resources.
None—This option conserves logic resources by eliminating multiply hardware.
Multiply operations are implemented in software.
Figure
4–1, the Core Nios II page displays a “selector guide” table that
Nios II Core Implementation Details
Nios II Core Implementation Details
Nios II Processor Reference Handbook
chapter of the Nios II
4–3