IPR-NIOS Altera, IPR-NIOS Datasheet - Page 23

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

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NII51002-10.1.0
Introduction
Nios II Processor Reference Handbook
December 2010
December 2010
NII51002-10.1.0
This chapter describes the hardware structure of the Nios
discussion of all the functional units of the Nios II architecture and the fundamentals
of the Nios II processor hardware implementation. This chapter contains the
following sections:
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The Nios II architecture describes an instruction set architecture (ISA). The ISA in turn
necessitates a set of functional units that implement the instructions. A Nios II
processor core is a hardware design that implements the Nios II instruction set and
supports the functional units described in this document. The processor core does not
include peripherals or the connection logic to the outside world. It includes only the
circuits required to implement the Nios II architecture.
Figure 2–1
The Nios II architecture defines the following functional units:
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“Processor Implementation” on page 2–2
“Register File” on page 2–3
“Arithmetic Logic Unit” on page 2–4
“Reset and Debug Signals” on page 2–8
“Exception and Interrupt Controllers” on page 2–8
“Memory and I/O Organization” on page 2–11
“JTAG Debug Module” on page 2–18
Register file
Arithmetic logic unit (ALU)
Interface to custom instruction logic
Exception controller
Internal or external interrupt controller
Instruction bus
Data bus
Memory management unit (MMU)
Memory protection unit (MPU)
Instruction and data cache memories
Tightly-coupled memory interfaces for instructions and data
JTAG debug module
shows a block diagram of the Nios II processor core.
2. Processor Architecture
®
II processor, including a
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