IPR-NIOS Altera, IPR-NIOS Datasheet - Page 153

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 5: Nios II Core Implementation Details
Nios II/e Core
December 2010 Altera Corporation
Memory Access
Instruction Execution Stages
Instruction Performance
Exception Handling
f
The Nios II/e core does not provide instruction cache or data cache. All memory and
peripheral accesses generate an Avalon-MM transfer. The Nios II/e core can address
up to 2 GB of external memory. The Nios II architecture reserves the most-significant
bit of data addresses for the bit-31 cache bypass method. In the Nios II/e core, bit 31 is
always zero.
For information regarding data cache bypass methods, refer to the
Architecture
This section provides an overview of the pipeline behavior as a means of estimating
assembly execution time. Most application programmers never need to analyze the
performance of individual instructions.
The Nios II/e core dispatches a single instruction at a time, and the processor waits
for an instruction to complete before fetching and dispatching the next instruction.
Because each instruction completes before the next instruction is dispatched, branch
prediction is not necessary. This greatly simplifies the consideration of processor
stalls. Maximum performance is one instruction per six clock cycles. To achieve six
cycles, the Avalon-MM instruction master port must fetch an instruction in one clock
cycle. A stall on the Avalon-MM instruction master port directly extends the execution
time of the instruction.
Execution performance for all instructions is shown in
Table 5–16. Instruction Execution Performance for Nios II/e Core
The Nios II/e core supports the following exception types:
Normal ALU instructions (e.g., add, cmplt)
branch, jmp, jmpi, ret, call, callr
trap, break, eret, bret,
flushp, wrctl, rdctl,
unimplemented
load word
load halfword
load byte
store
Shift, rotate
All other instructions
Combinatorial custom instructions
Multi-cycle custom instructions
chapter of the Nios II Processor Reference Handbook.
Instruction
6
6
6
6 + Duration of Avalon-MM read transfer
9 + Duration of Avalon-MM read transfer
10 + Duration of Avalon-MM read transfer
6 + Duration of Avalon-MM write transfer
7 to 38
6
6
Š6
Table
Nios II Processor Reference Handbook
Cycles
5–16.
Processor
5–21