IPR-NIOS Altera, IPR-NIOS Datasheet - Page 209

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 8: Instruction Set Reference
Instruction Set Reference
break
December 2010 Altera Corporation
Operation:
Assembler Syntax:
Example:
Description:
Usage:
Exceptions:
Instruction Type:
Instruction Fields:
31
30
29
0
28
27
26
25
24
0
bstatus ← status
PIE ← 0
U ← 0
ba ← PC + 4
PC ← break handler address
break
break imm5
break
Breaks program execution and transfers control to the debugger break-processing routine.
Saves the address of the next instruction in register ba and saves the contents of the status
register in bstatus. Disables interrupts, then transfers execution to the break handler.
The 5-bit immediate field imm5 is ignored by the processor, but it can be used by the debugger.
break with no argument is the same as break 0.
break is used by debuggers exclusively. Only debuggers should place break in a user
program, operating system, or exception handler. The address of the break handler is specified
at system generation time.
Some debuggers support break and break 0 instructions in source code. These debuggers
treat the break instruction as a normal breakpoint.
Break
R
IMM5 = Type of breakpoint
23
22
21
20
0x1e
19
18
17
16
15
14
0x34
13
12
11
10
9
IMM5
8
Nios II Processor Reference Handbook
debugging breakpoint
7
6
5
4
0x3a
3
2
1
8–23
0