IPR-NIOS Altera, IPR-NIOS Datasheet - Page 32

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

2–10
Table 2–5. Interrupt Vector Custom Instruction
Nios II Processor Reference Handbook
ALT_CI_EXCEPTION_VECTOR_N
Operation:
Assembler Syntax:
Example:
Description:
Usage:
Exceptions:
Instruction Type:
Instruction Fields:
31
30
29
0
28
f
1
27
26
Interrupt Vector Custom Instruction
The Nios II processor core offers an interrupt vector custom instruction which
accelerates interrupt vector dispatch. Include this custom instruction to reduce your
program’s interrupt latency.
The interrupt vector custom instruction is based on a priority encoder with one input
for each interrupt connected to the Nios II processor. The cost of the interrupt vector
custom instruction depends on the number of interrupts connected to the Nios II
processor. The worst case is a system with 32 interrupts. In this case, the interrupt
vector custom instruction consumes about 50 logic elements (LEs).
If you have a large number of interrupts connected, adding the interrupt vector
custom instruction to your system might lower f
For guidance in adding the interrupt vector custom instruction to the Nios II
processor, refer to the
Nios II Processor Reference Handbook.
The interrupt vector custom instruction is not compatible with the EIC interface. For
the Nios II/f core, the EIC interface with the Altera vectored interrupt controller
component provides superior performance.
Table 2–5
For an explanation of the instruction reference format, refer to the
Reference
25
24
0
if (ipending == 0) | (estatus.PIE == 0)
custom ALT_CI_EXCEPTION_VECTOR_N, rC, r0, r0
custom ALT_CI_EXCEPTION_VECTOR_N, et, r0, r0
blt et, r0, not_irq
The interrupt vector custom instruction accelerates interrupt vector dispatch. This custom
instruction identifies the highest priority interrupt, generates the vector table offset, and stores
this offset to rC. The instruction generates a negative offset if there is no hardware interrupt
(that is, the exception is caused by a software condition, such as a trap).
The interrupt vector custom instruction is used exclusively by the exception handler.
None
R
C = Register index of operand rC
N = Value of ALT_CI_EXCEPTION_VECTOR_N
23
then rC ← negative value
else rC ← 8 × bit # of the least-significant 1 bit of the ipending register (ctl4)
chapter of the Nios II Processor Reference Handbook.
details the implementation of the interrupt vector custom instruction.
22
21
20
19
C
Instantiating the Nios II Processor in SOPC Builder
18
17
16
0 0 1
15
14
13
12
11
MAX
10
N
.
9
8
December 2010 Altera Corporation
Chapter 2: Processor Architecture
7
Exception and Interrupt Controllers
6
Instruction Set
5
4
chapter of the
0x32
3
2
1
0