IPR-NIOS Altera, IPR-NIOS Datasheet - Page 90

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–44
Nios II Processor Reference Handbook
f
1
Processing General Exceptions
The general exception handler is a routine that determines the cause of each exception
(including the double TLB miss exception), and then dispatches an exception routine
to respond to the exception. The address of the general exception handler, specified in
SOPC Builder at system generation time, is called the exception vector in the Nios II
Processor parameter editor. At run time this address is fixed, and software cannot
modify it. Programmers do not directly access exception vectors, and can write
programs without awareness of the address.
If the EIC interface is present, the general exception handler processes only
noninterrupt exceptions.
The fast TLB miss exception handler only handles the fast TLB miss exception. It is
built for speed to process TLB misses quickly. The fast TLB miss exception handler
address, specified in SOPC Builder at system generation time, is called the fast TLB
miss exception vector in the Nios II Processor parameter editor.
Exception Flow with the EIC Interface
If the EIC interface is present, interrupt processing differs markedly from
noninterrupt exception processing. The EIC interface provides the following
information to the Nios II processor for each interrupt request:
■
■
■
■
For further information about the RHA, RRS, RIL and RNMI, refer to “The Nios II/f
Core” in the
Handbook.
When the EIC interface presents an interrupt to the Nios II processor, the processor
uses several criteria, as follows, to determine whether to take the interrupt:
■
■
RHA—The requested handler address for the interrupt handler assigned to the
requested interrupt.
RRS—The requested register set to be used when the interrupt handler executes. If
shadow register sets are not implemented, RRS must always be 0.
RIL—The requested interrupt level specifies the priority of the interrupt.
RNMI—The requested NMI flag specifies whether to treat the interrupt as
nonmaskable.
Nonmaskable interrupts—The processor takes any NMI as long as it is not
processing a previous NMI.
Maskable interrupts—The processor takes a maskable interrupt if maskable
interrupts are enabled, and if the requested interrupt level is higher than that of
the interrupt currently being processed (if any). However, if shadow register sets
are implemented, the processor takes the interrupt only if the interrupt requests a
register set different from the current register set, or if the register set interrupt
enable flag (status.RSIE) is set.
Nios II Core Implementation Details
chapter of the Nios II Processor Reference
December 2010 Altera Corporation
Chapter 3: Programming Model
Exception Processing