IPR-NIOS Altera, IPR-NIOS Datasheet - Page 148

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

5–16
Table 5–12. Hardware Multiply and Divide Details for the Nios II/s Core
Nios II Processor Reference Handbook
No hardware multiply or divide
LE-based multiplier
Embedded multiplier on
Stratix II and Stratix III families
Embedded multiplier on
Cyclone II and Cyclone III
families
Hardware divide
Memory Access
ALU Option
f
1
The performance of the embedded multipliers differ, depending on the target FPGA
family.
Table 5–12
Shift and Rotate Performance
The performance of shift operations depends on the hardware multiply option. When
a hardware multiplier is present, the ALU achieves shift and rotate operations in three
or four clock cycles. Otherwise, the ALU includes dedicated shift circuitry that
achieves one-bit-per-cycle shift and rotate performance. Refer to
page 5–19
The Nios II/s core provides instruction cache, but no data cache. The instruction
cache size is user-definable, between 512 bytes and 64 KB. The Nios II/s core can
address up to 2 gigabytes (GB) of external memory. The Nios II architecture reserves
the most-significant bit of data addresses for the bit-31 cache bypass method. In the
Nios II/s core, bit 31 is always zero.
For information regarding data cache bypass methods, refer to the
Architecture
Instruction and Data Master Ports
The instruction port on the Nios II/s core is optional. The instruction master port can
be excluded, as long as the core includes at least one tightly-coupled instruction
memory. The instruction master port is a pipelined Avalon-MM master port.
Support for pipelined Avalon-MM transfers minimizes the impact of synchronous
memory with pipeline latency. The pipelined instruction master port can issue
successive read requests before prior requests complete.
The data master port on the Nios II/s core is always present.
Multiply and divide instructions
generate an exception
ALU includes 32 x 4-bit
multiplier
ALU includes 32 x 32-bit
multiplier
ALU includes 32 x 16-bit
multiplier
ALU includes multicycle divide
circuit
for details.
lists the details of the hardware multiply and divide options.
chapter of the Nios II Processor Reference Handbook.
Hardware Details
instruction
Cycles per
4 – 66
11
–
3
5
Chapter 5: Nios II Core Implementation Details
None
mul, muli
mul, muli, mulxss, mulxsu,
mulxuu
mul, muli
div, divu
December 2010 Altera Corporation
Supported Instructions
Table 5–15 on
Processor
Nios II/s Core