IPR-NIOS Altera, IPR-NIOS Datasheet - Page 66

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–20
Nios II Processor Reference Handbook
The DBL Flag
During a general exception, the processor sets DBL to one when a double TLB miss
condition exists. Otherwise, the processor clears DBL to zero.
The DBL flag indicates whether the most recent exception is a double TLB miss
condition. When a general exception occurs, the MMU sets DBL to one if a double TLB
miss is detected, and clears DBL to zero otherwise.
The BAD Flag
During a general exception, the processor sets BAD to one when a bad virtual address
condition exists, and clears BAD to zero otherwise. The following exceptions set the BAD
flag to one:
■
■
■
■
Refer to
The PERM Flag
During a general exception, the processor sets PERM to one for a TLB permission
violation exception, and clears PERM to zero otherwise.
The D Flag
The D flag indicates whether the exception is an instruction access exception or a data
access exception. During a general exception, the processor sets D to one when the
exception is related to a data access, and clears D to zero for all other nonbreak
exceptions.
The following exceptions set the D flag to one:
■
■
■
■
■
The badaddr Register
When the extra exception information option is enabled, the Nios II processor
provides information useful to system software for exception processing in the
exception and badaddr registers when an exception occurs. When your system
contains an MMU or MPU, the extra exception information is always enabled. When
no MMU or MPU is present, the Nios II Processor parameter editor gives you the
option to have the processor provide the extra exception information.
To see how to control the extra exception information option, refer to the
the Nios II Processor in SOPC Builder
Supervisor-only instruction address
Supervisor-only data address
Misaligned data address
Misaligned destination address
Fast TLB miss (data)
Double TLB miss (data)
TLB permission violation (read or write)
Misaligned data address
Supervisor-only data address
Table 3–33 on page 3–32
for more information on these exceptions.
chapter of the Nios II Processor Reference Handbook.
December 2010 Altera Corporation
Chapter 3: Programming Model
Instantiating
Registers