IPR-NIOS Altera, IPR-NIOS Datasheet - Page 36

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

2–14
Nios II Processor Reference Handbook
Cache Memory
The Nios II architecture supports on-chip cache memory for improving average data
transfer performance when accessing slower memory. Refer to
page 2–14
which provides guaranteed low-latency access to on-chip memory. Refer to
“Tightly-Coupled Memory” on page 2–15
Shared Memory for Instructions and Data
Usually the instruction and data master ports share a single memory that contains
both instructions and data. While the processor core has separate instruction and data
buses, the overall Nios II processor system might present a single, shared
instruction/data bus to the outside world. The outside view of the Nios II processor
system depends on the memory and peripherals in the system and the structure of the
system interconnect fabric.
The data and instruction master ports never cause a gridlock condition in which one
port starves the other. For highest performance, assign the data master port higher
arbitration priority on any memory that is shared by both instruction and data master
ports.
The Nios II architecture supports cache memories on both the instruction master port
(instruction cache) and the data master port (data cache). Cache memory resides
on-chip as an integral part of the Nios II processor core. The cache memories can
improve the average memory access time for Nios II processor systems that use slow
off-chip memory such as SDRAM for program and data storage.
The instruction and data caches are enabled perpetually at run-time, but methods are
provided for software to bypass the data cache so that peripheral accesses do not
return cached data. Cache management and cache coherency are handled by software.
The Nios II instruction set provides instructions for cache management.
Configurable Cache Memory Options
The cache memories are optional. The need for higher memory performance (and by
association, the need for cache memory) is application dependent. Many applications
require the smallest possible processor core, and can trade-off performance for size.
A Nios II processor core might include one, both, or neither of the cache memories.
Furthermore, for cores that provide data and/or instruction cache, the sizes of the
cache memories are user-configurable. The inclusion of cache memory does not affect
the functionality of programs, but it does affect the speed at which the processor
fetches instructions and reads/writes data.
Effective Use of Cache Memory
The effectiveness of cache memory to improve performance is based on the following
premises:
■
■
Regular memory is located off-chip, and access time is long compared to on-chip
memory
The largest, performance-critical instruction loop is smaller than the instruction
cache
for details. The Nios II architecture supports tightly-coupled memory,
for details.
December 2010 Altera Corporation
Chapter 2: Processor Architecture
“Cache Memory” on
Memory and I/O Organization