IPR-NIOS Altera, IPR-NIOS Datasheet - Page 70

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–24
Table 3–27. mpuacc Control Register Field Descriptions (Part 2 of 2)
Nios II Processor Reference Handbook
RD
WR
Note to
(1) The MASK and LIMIT fields are mutually exclusive. Refer to
Field
Table
3–27:
1
RD is the read region flag. When RD = 1, wrctl instructions to the
mpuacc register perform a read operation.
WR is the write region flag. When WR = 1, wrctl instructions to the
mpuacc register perform a write operation.
The following sections provide further details of the mpuacc fields.
The MASK Field
When the amount of memory reserved for a region is defined by size, the MASK field
specifies the size of the memory region. The MASK field is the same number of bits as
the BASE field of the mpubase register.
Unused high-order or low-order bits must be written as zero and are read as zero.
Table 3–28
byte address space.
Table 3–28. MASK Region Size Encodings (Part 1 of 2)
shows the MASK field encodings for all possible region sizes in a full 31-bit
MASK Encoding
0x1FFFFFF
0x1FFFFFE
0x1FFFFFC
0x1FFFFF8
0x1FFFFF0
0x1FFFFE0
0x1FFFFC0
0x1FFFF80
0x1FFFF00
0x1FFFE00
0x1FFFC00
0x1FFF800
0x1FFF000
0x1FFE000
0x1FFC000
0x1FF8000
0x1FF0000
0x1FE0000
0x1FC0000
0x1F80000
0x1F00000
Description
Table 3–25
and
Table
3–26.
Access
Write
Write
Region Size
December 2010 Altera Corporation
128 bytes
256 bytes
512 bytes
64 bytes
128 KB
256 KB
512 KB
16 MB
32 MB
64 MB
16 KB
32 KB
64 KB
1 MB
2 MB
4 MB
8 MB
Chapter 3: Programming Model
1 KB
2 KB
4 KB
8 KB
Reset
0
0
Available
Only with
Only with
MPU
MPU
Registers