IPR-NIOS Altera, IPR-NIOS Datasheet - Page 140

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

5–8
Table 5–6. Cache Virtual Byte Address Fields
Table 5–7. Cache Physical Byte Address Fields
Nios II Processor Reference Handbook
31
31
30
30
29
29
28
28
27
27
26
26
Table 5–6
present.
MMU present.
Instruction Cache
The instruction cache memory has the following characteristics:
■
■
■
■
■
The size of the tag field depends on the size of the cache memory and the physical
address size. The size of the line field depends only on the size of the cache memory.
The offset field is always five bits (i.e., a 32-byte line). The maximum instruction byte
address size is 31 bits in systems without an MMU present. In systems with an MMU,
the maximum instruction byte address size is 32 bits and the tag field always includes
all the bits of the physical frame number (PFN).
The instruction cache is optional. However, excluding instruction cache from the
Nios II/f core requires that the core include at least one tightly-coupled instruction
memory.
Data Cache
The data cache memory has the following characteristics:
■
■
■
■
■
■
25
25
tag
Direct-mapped cache implementation.
32 bytes (8 words) per cache line.
The instruction master port reads an entire cache line at a time from memory, and
issues one read per clock cycle.
Critical word first.
Virtually-indexed, physically-tagged, when MMU present.
Direct-mapped cache implementation
Configurable line size of 4, 16, or 32 bytes
The data master port reads an entire cache line at a time from memory, and issues
one read per clock cycle.
Write-back
Write-allocate (i.e., on a store instruction, a cache miss allocates the line for that
address)
Virtually-indexed, physically-tagged, when MMU present
24
24
23
23
Table 5–7
shows the cache virtual byte address fields for systems with an MMU
22
22
21
21
20
20
shows the cache physical byte address fields for systems with an
19
19
18
18
17
17
16
16
15
15
14
14
13
13
line
12
12
11
11
10
10
Chapter 5: Nios II Core Implementation Details
9
9
8
8
December 2010 Altera Corporation
7
7
6
6
5
5
4
4
3
3
offset
offset
Nios II/f Core
2
2
1
1
0
0