IPR-NIOS Altera, IPR-NIOS Datasheet - Page 88

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–42
Nios II Processor Reference Handbook
Fast TLB Miss
Fast TLB miss exceptions are implemented only in Nios II processors that include the
MMU. The MMU has a special exception vector (fast TLB miss), specified in SOPC
Builder at system generation time, specifically to handle TLB miss exceptions quickly.
Whenever the processor cannot find a TLB entry matching the VPN (optionally
extended by a process identifier), the result is a TLB miss exception. At the time of the
exception, the processor first checks status.EH. When status.EH = 0, no other
exception is already in process, so the processor considers the TLB miss a fast TLB
miss, sets status.EH to one, and transfers control to the fast TLB miss exception
handler (rather than to the general exception handler).
There are two kinds of fast TLB miss exceptions:
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The fast TLB miss exception handler can inspect the tlbmisc.D field to determine
which kind of fast TLB miss exception occurred.
Double TLB Miss
Double TLB miss exceptions are implemented only in Nios II processors that include
the MMU. When a TLB miss exception occurs while software is currently processing
an exception (that is, when status.EH = 1), a double TLB miss exception is generated.
Specifically, whenever the processor cannot find a TLB entry matching the VPN
(optionally extended by a process identifier) and status.EH = 1, the result is a double
TLB miss exception. The most common scenario is that a double TLB miss exception
occurs during processing of a fast TLB miss exception. The processor preserves
register values from the original exception and transfers control to the general
exception handler which processes the newly-generated exception.
There are two kinds of double TLB miss exceptions:
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The general exception handler can inspect either the exception.CAUSE or tlbmisc.D
field to determine which kind of double TLB miss exception occurred.
TLB Permission Violation
TLB permission violation exceptions are implemented only in Nios II processors that
include the MMU. When a TLB entry is found matching the VPN (optionally
extended by a process identifier), but the permissions do not allow the access to
complete, a TLB permission violation exception is generated.
There are three kinds of TLB permission violation exceptions:
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Fast TLB miss (instruction)—Any instruction fetch can cause this exception.
Fast TLB miss (data)—Load, store, initda, and flushda instructions can cause this
exception.
Double TLB miss (instruction)—Any instruction fetch can cause this exception.
Double TLB miss (data)—Load, store, initda, and flushda instructions can cause
this exception.
TLB permission violation (execute)—Any instruction fetch can cause this
exception.
TLB permission violation (read)—Any load instruction can cause this exception.
TLB permission violation (write)—Any store instruction can cause this exception.
December 2010 Altera Corporation
Chapter 3: Programming Model
Exception Processing