IPR-NIOS Altera, IPR-NIOS Datasheet - Page 242

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

8–56
initda
Nios II Processor Reference Handbook
Operation:
Assembler Syntax:
Example:
Description:
Usage:
Exceptions:
Instruction Type:
Instruction Fields:
31
30
29
A
28
27
26
25
24
0
Initializes the data cache line currently caching address rA + σ (IMM16)
initda IMM16(rA)
initda -100(r6)
If the Nios II processor implements a direct mapped data cache, initda clears the data cache
line without checking for (or writing) a dirty data cache line that is mapped to the specified
address back to memory. Unlike initd, initda clears the cache line only when the addressed
data is currently cached. This process comprises the following steps:
■
■
■
■
■
If the Nios II processor core does not have a data cache, the initda instruction performs no
operation.
Use initda to skip writing dirty lines back to memory and to flush the cache line only if the
addressed memory location is currently in the cache. By contrast, refer to
cache line” on page
data cache line” on page 8–55
because it does not write back dirty data.
For more information on the Nios II data cache, refer to the
chapter of the Nios II Software Developer’s Handbook.
Supervisor-only data address
Fast TLB miss (data)
Double TLB miss (data)
MPU region violation (data)
Unimplemented instruction
I
A = Register index of operand rA
IMM16 = 16-bit signed immediate value
Compute the effective address specified by the sum of rA and the signed 16-bit immediate
value.
Identify the data cache line associated with the computed effective address. Each data cache
effective address comprises a tag field and a line field. When identifying the line, initda
uses both the tag field and the line field.
Compare the cache line tag with the effective address to determine if the addressed data is
currently cached. If the tag fields do not match, the effective address is not currently
cached, so the instruction does nothing.
Skip checking if the data cache line is dirty. Because initd skips the dirty cache line check,
data that has been modified by the processor, but not yet written to memory is lost.
Clear the valid bit for the line.
23
22
21
20
19
8–51,
18
“flushda flush data cache address” on page
17
16
for other cache-clearing options. Use initda with caution
15
IMM16
14
13
12
11
10
initialize data cache address
9
Cache and Tightly Coupled Memory
8
Chapter 8: Instruction Set Reference
December 2010 Altera Corporation
7
8–52, and
6
5
“flushd flush data
Instruction Set Reference
4
“initd initialize
0x13
3
2
1
0