IPR-NIOS Altera, IPR-NIOS Datasheet - Page 52

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–6
Nios II Processor Reference Handbook
TLB Organization
f
1
Data Cacheability
Each partition has a rule that determines the default data cacheability property of
each memory access. When data cacheability is enabled on a partition of the address
space, a data access to that partition can be cached, if a data cache is present in the
system. When data cacheability is disabled, all access to that partition goes directly to
the Avalon switch fabric. Bit 31 is not used to specify data cacheability, as it is in
Nios II cores without MMUs. Virtual memory partitions that bypass the TLB have a
default data cacheability property, as shown in
mapped through the TLB, data cacheability is controlled by the TLB on a per-page
basis.
Non-I/O load and store instructions use the default data cacheability property. I/O
load and store instructions are always noncacheable, so they ignore the default data
cacheability property.
A TLB functions as a cache for the operating system’s page table. In Nios II processors
with an MMU, one main TLB is shared by instruction and data accesses. The TLB is
stored in on-chip RAM and handles translations for instruction fetches and
instructions that perform data accesses.
The TLB is organized as an n-way set-associative cache. The software specifies the
way (set) when loading a new entry.
You can configure the number of TLB entries and the number of ways (set
associativity) of the TLB in SOPC Builder at system generation time. By default, the
TLB is a 16-way cache. The default number of entries depends on the target device, as
follows:
The operating system software is responsible for guaranteeing that multiple TLB
entries do not map the same virtual address. The hardware behavior is undefined
when multiple entries map the same virtual address.
Each TLB entry consists of a tag and data portion. This is analogous to the tag and
data portion of instruction and data caches.
Refer to the
Handbook for details on instruction and data caches.
■
■
Cyclone
Cyclone III, Stratix III, Stratix IV—256 entries, requiring one M9K RAM
For further detail, refer to the
chapter of the Nios II Processor Reference Handbook.
Nios II Core Implementation Details
®
II, Stratix
®
II, Stratix II GX—128 entries, requiring one M4K RAM
Instantiating the Nios II Processor in SOPC Builder
chapter of the Nios II Processor Reference
Table
3–2. For partitions that are
December 2010 Altera Corporation
Chapter 3: Programming Model
Memory Management Unit