IPR-NIOS Altera, IPR-NIOS Datasheet - Page 250

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

8–64
ldw / ldwio
Nios II Processor Reference Handbook
Operation:
Assembler Syntax:
Example:
Description:
Usage:
Exceptions:
Instruction Type:
Instruction Fields:
31
31
30
30
29
29
A
A
28
28
27
27
26
26
25
25
24
24
B
B
rB ← Mem32[rA + σ (IMM14)]
ldw rB, byte_offset(rA)
ldwio rB, byte_offset(rA)
ldw r6, 100(r5)
Computes the effective byte address specified by the sum of rA and the instruction's signed
16-bit immediate value. Loads register rB with the memory word located at the effective byte
address. The effective byte address must be word aligned. If the byte address is not a multiple
of 4, the operation is undefined.
In processors with a data cache, this instruction may retrieve the desired data from the cache
instead of from memory. Use the ldwio instruction for peripheral I/O. In processors with a data
cache, ldwio bypasses the cache and memory. Use the ldwio instruction for peripheral I/O. In
processors with a data cache, ldwio bypasses the cache and is guaranteed to generate an
Avalon-MM data transfer. In processors without a data cache, ldwio acts like ldw.
For more information on data cache, refer to the
the Nios II Software Developer’s Handbook.
Supervisor-only data address
Misaligned data address
TLB permission violation (read)
Fast TLB miss (data)
Double TLB miss (data)
MPU region violation (data)
I
A = Register index of operand rA
B = Register index of operand rB
IMM16 = 16-bit signed immediate value
23
23
22
22
21
21
20
20
19
19
Instruction format for ldwio
Instruction format for ldw
18
18
17
17
load 32
16
16
15
15
IMM16
IMM16
14
14
-
bit word from memory or I/O peripheral
13
13
12
12
Cache and Tightly Coupled Memory
11
11
10
10
9
9
8
8
Chapter 8: Instruction Set Reference
December 2010 Altera Corporation
7
7
6
6
5
5
Instruction Set Reference
4
4
0x17
0x37
3
3
chapter of
2
2
1
1
0
0