LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 14

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
2.3 APB peripheral addresses
UM10360
User manual
Figure 3
peripheral area is 2 megabyte in size, and is divided to allow for up to 128 peripherals.
The APB peripheral area is 1 megabyte in size and is divided to allow for up to 64
peripherals. Each peripheral of either type is allocated 16 kilobytes of space. This allows
simplifying the address decoding for each peripheral.
All peripheral register addresses are word aligned (to 32-bit boundaries) regardless of
their size. This eliminates the need for byte lane mapping hardware that would be required
to allow byte (8-bit) or half-word (16-bit) accesses to occur at smaller boundaries. An
implication of this is that word and half-word registers must be accessed all at once. For
example, it is not possible to read or write the upper byte of a word register separately.
The following table shows the APB0/1 address maps. No APB peripheral uses all of the
16 kB space allocated to it. Typically each device’s registers are "aliased" or repeated at
multiple locations within each 16 kB range.
Table 4.
APB0 peripheral
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19 to 22
23
24 to 31
and
APB0 peripherals and base addresses
Table 4
All information provided in this document is subject to legal disclaimers.
Base address
0x4000 0000
0x4000 4000
0x4000 8000
0x4000 C000
0x4001 0000
0x4001 4000
0x4001 8000
0x4001 C000
0x4002 0000
0x4002 4000
0x4002 8000
0x4002 C000
0x4003 0000
0x4003 4000
0x4003 8000
0x4003 C000
0x4004 0000
0x4004 4000
0x4004 8000
0x4004 C000 to 0x4005 8000
0x4005 C000
0x4006 0000 to 0x4007 C000
show different views of the peripheral address space. The AHB
Rev. 2 — 19 August 2010
Peripheral name
Watchdog Timer
Timer 0
Timer 1
UART0
UART1
reserved
PWM1
I
SPI
RTC
GPIO interrupts
Pin Connect Block
SSP1
ADC
CAN Acceptance Filter RAM
CAN Acceptance Filter Registers
CAN Common Registers
CAN Controller 1
CAN Controller 2
reserved
I
reserved
2
2
Chapter 2: LPC17xx Memory map
C0
C1
UM10360
© NXP B.V. 2010. All rights reserved.
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