LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 83

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 58.
UM10360
User manual
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Name
ICP_WDT
ICP_TIMER0
ICP_TIMER1
ICP_TIMER2
ICP_TIMER3
ICP_UART0
ICP_UART1
ICP_UART2
ICP_UART3
ICP_PWM
ICP_I2C0
ICP_I2C1
ICP_I2C2
ICP_SPI
ICP_SSP0
ICP_SSP1
ICP_PLL0
ICP_RTC
ICP_EINT0
ICP_EINT1
ICP_EINT2
ICP_EINT3
ICP_ADC
ICP_BOD
ICP_USB
ICP_CAN
ICP_DMA
ICP_I2S
ICP_ENET
ICP_RIT
ICP_MCPWM
ICP_QEI
Interrupt Clear-Pending Register 0 register (ICPR0 - 0xE000 E280)
6.5.7 Interrupt Clear-Pending Register 0 register (ICPR0 - 0xE000 E280)
Function
Watchdog Timer Interrupt Pending clear.
Write: writing 0 has no effect, writing 1 changes the interrupt state to not pending.
Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending.
Timer 0 Interrupt Pending clear. See functional description for bit 0.
Timer 1. Interrupt Pending clear. See functional description for bit 0.
Timer 2 Interrupt Pending clear. See functional description for bit 0.
Timer 3 Interrupt Pending clear. See functional description for bit 0.
UART0 Interrupt Pending clear. See functional description for bit 0.
UART1 Interrupt Pending clear. See functional description for bit 0.
UART2 Interrupt Pending clear. See functional description for bit 0.
UART3 Interrupt Pending clear. See functional description for bit 0.
PWM1 Interrupt Pending clear. See functional description for bit 0.
I
I
I
SPI Interrupt Pending clear. See functional description for bit 0.
SSP0 Interrupt Pending clear. See functional description for bit 0.
SSP1 Interrupt Pending clear. See functional description for bit 0.
PLL0 (Main PLL) Interrupt Pending clear. See functional description for bit 0.
Real Time Clock (RTC) Interrupt Pending clear. See functional description for bit 0.
External Interrupt 0 Interrupt Pending clear. See functional description for bit 0.
External Interrupt 1 Interrupt Pending clear. See functional description for bit 0.
External Interrupt 2 Interrupt Pending clear. See functional description for bit 0.
External Interrupt 3 Interrupt Pending clear. See functional description for bit 0.
ADC Interrupt Pending clear. See functional description for bit 0.
BOD Interrupt Pending clear. See functional description for bit 0.
USB Interrupt Pending clear. See functional description for bit 0.
CAN Interrupt Pending clear. See functional description for bit 0.
GPDMA Interrupt Pending clear. See functional description for bit 0.
I
Ethernet Interrupt Pending clear. See functional description for bit 0.
Repetitive Interrupt Timer Interrupt Pending clear. See functional description for bit 0.
Motor Control PWM Interrupt Pending clear. See functional description for bit 0.
Quadrature Encoder Interface Interrupt Pending clear. See functional description for bit 0.
The ICPR0 register allows clearing the pending state of the first 32 peripheral interrupts,
or for reading the pending state of those interrupts. The remaining interrupts can have
their pending state cleared via the ICPR1 register
state of interrupts is done through the ISPR0 and ISPR1 registers
Section
2
2
2
2
C0 Interrupt Pending clear. See functional description for bit 0.
C1 Interrupt Pending clear. See functional description for bit 0.
C2 Interrupt Pending clear. See functional description for bit 0.
S Interrupt Pending clear. See functional description for bit 0.
6.5.6).
All information provided in this document is subject to legal disclaimers.
Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC)
Rev. 2 — 19 August 2010
(Section
6.5.8). Setting the pending
(Section 6.5.5
UM10360
© NXP B.V. 2010. All rights reserved.
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