LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 425

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
UM10360
User manual
18.6.7 SSPn Raw Interrupt Status Register (SSP0RIS - 0x4008 8018,
18.6.8 SSPn Masked Interrupt Status Register (SSP0MIS - 0x4008 801C,
Table 375: SSPn Interrupt Mask Set/Clear register (SSP0IMSC - address 0x4008 8014,
SSP1RIS - 0x4003 0018)
This read-only register contains a 1 for each interrupt condition that is asserted,
regardless of whether or not the interrupt is enabled in the SSPnIMSC.
Table 376: SSPn Raw Interrupt Status register (SSP0RIS - address 0x4008 8018, SSP1RIS -
SSP1MIS - 0x4003 001C)
This read-only register contains a 1 for each interrupt condition that is asserted and
enabled in the SSPnIMSC. When an SSP interrupt occurs, the interrupt service routine
should read this register to determine the cause(s) of the interrupt.
Bit
0
1
2
3
31:4
Bit
0
1
2
3
31:4
Symbol Description
RORIM
RTIM
RXIM
TXIM
-
Symbol
RORRIS This bit is 1 if another frame was completely received while the RxFIFO
RTRIS
RXRIS
TXRIS
-
SSP1IMSC - 0x4003 0014) bit description
0x4003 0018) bit description
All information provided in this document is subject to legal disclaimers.
Software should set this bit to enable interrupt when a Receive Overrun
occurs, that is, when the Rx FIFO is full and another frame is completely
received. The ARM spec implies that the preceding frame data is
overwritten by the new frame data when this occurs.
Software should set this bit to enable interrupt when a Receive Timeout
condition occurs. A Receive Timeout occurs when the Rx FIFO is not
empty, and no has not been read for a "timeout period". The timeout
period is the same for master and slave modes and is determined by the
SSP bit rate: 32 bits at PCLK / (CPSDVSR × [SCR+1]).
Software should set this bit to enable interrupt when the Rx FIFO is at
least half full.
Software should set this bit to enable interrupt when the Tx FIFO is at
least half empty.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Description
was full. The ARM spec implies that the preceding frame data is
overwritten by the new frame data when this occurs.
This bit is 1 if the Rx FIFO is not empty, and has not been read for a
"timeout period". The timeout period is the same for master and slave
modes and is determined by the SSP bit rate: 32 bits at PCLK /
(CPSDVSR × [SCR+1]).
This bit is 1 if the Rx FIFO is at least half full.
This bit is 1 if the Tx FIFO is at least half empty.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Rev. 2 — 19 August 2010
Chapter 18: LPC17xx SSP0/1
UM10360
© NXP B.V. 2010. All rights reserved.
425 of 840
Reset
Value
0
0
0
0
NA
Reset
Value
0
0
0
1
NA