LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 95
LPC1769FBD100,551
Manufacturer Part Number
LPC1769FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.OM11043.pdf
(79 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
4.LPC1769FBD100551.pdf
(66 pages)
Specifications of LPC1769FBD100,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
100-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4966
935290522551
935290522551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1769FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
Table 73.
UM10360
User manual
Symbol
P0[0] to P0[31]
P0[0] / RD1 /
TXD3 / SDA1
P0[1] / TD1 /
RXD3 / SCL1
P0[2] / TXD0 /
AD0[7]
P0[3] / RXD0 /
AD0[6]
P0[4] /
I2SRX_CLK /
RD2 / CAP2[0]
P0[5] / I2SRX_WS /
TD2 / CAP2[1]
P0[6] /
I2SRX_SDA /
SSEL1 / MAT2[0]
P0[7] /
I2STX_CLK /
SCK1 / MAT2[1]
Pin description
LQFP
100
46
47
98
99
81
80
79
78
LQFP
80
37
38
79
80
-
-
64
63
Type Description
I/O
I/O
I
O
I/O
I/O
O
I
I/O
I/O
O
I
I/O
I
I
I/O
I/O
I
I
I/O
I/O
O
I
I/O
I/O
I/O
O
I/O
I/O
I/O
O
All information provided in this document is subject to legal disclaimers.
Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each
bit. The operation of port 0 pins depends upon the pin function selected via
the pin connect block. Pins 12, 13, 14, and 31 of this port are not available.
P0[0] — General purpose digital input/output pin.
RD1 — CAN1 receiver input.
TXD3 — Transmitter output for UART3.
SDA1 — I
pad, see
P0[1] — General purpose digital input/output pin.
TD1 — CAN1 transmitter output.
RXD3 — Receiver input for UART3.
SCL1 — I
pad, see
P0[2] — General purpose digital input/output pin. When configured as an
ADC input, digital section of the pad is disabled.
TXD0 — Transmitter output for UART0.
AD0[7] — A/D converter 0, input 7.
P0[3] — General purpose digital input/output pin. When configured as an
ADC input, digital section of the pad is disabled.
RXD0 — Receiver input for UART0.
AD0[6] — A/D converter 0, input 6.
P0[4] — General purpose digital input/output pin.
I2SRX_CLK — Receive Clock. It is driven by the master and received by
the slave. Corresponds to the signal SCK in the I
RD2 — CAN2 receiver input.
CAP2[0] — Capture input for Timer 2, channel 0.
P0[5] — General purpose digital input/output pin.
I2SRX_WS — Receive Word Select. It is driven by the master and
received by the slave. Corresponds to the signal WS in the I
specification .
TD2 — CAN2 transmitter output.
CAP2[1] — Capture input for Timer 2, channel 1.
P0[6] — General purpose digital input/output pin.
I2SRX_SDA — Receive data. It is driven by the transmitter and read by
the receiver. Corresponds to the signal SD in the I
SSEL1 — Slave Select for SSP1.
MAT2[0] — Match output for Timer 2, channel 0.
P0[7] — General purpose digital input/output pin.
I2STX_CLK — Transmit Clock. It is driven by the master and received by
the slave. Corresponds to the signal SCK in the I
SCK1 — Serial Clock for SSP1.
MAT2[1] — Match output for Timer 2, channel 1.
Rev. 2 — 19 August 2010
Section 19.1
Section 19.1
2
2
C1 clock input/output (this pin does not use a specialized I2C
C1 data input/output (this pin does not use a specialized I2C
for details).
for details).
Chapter 7: LPC17xx Pin configuration
2
2
S bus specification .
S bus specification .
2
S bus specification .
UM10360
© NXP B.V. 2010. All rights reserved.
2
S bus
95 of 840
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