LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 224

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 193. USB Device Interrupt Status register (USBDevIntSt - address 0x5000 C200) bit description
Table 194. USB Device Interrupt Enable register (USBDevIntEn - address 0x5000 C204) bit allocation
Reset value: 0x0000 0000
Table 195. USB Device Interrupt Enable register (USBDevIntEn - address 0x5000 C204) bit description
Table 196. USB Device Interrupt Clear register (USBDevIntClr - address 0x5000 C208) bit allocation
Reset value: 0x0000 0000
UM10360
User manual
Bit
8
9
31:10 -
Bit
31:0
Bit
Symbol
Bit
Symbol
Bit
Symbol
Bit
Symbol
Bit
Symbol
Symbol
See
USBDevIntEn
bit allocation
table above
Symbol
EP_RLZED
ERR_INT
11.10.2.3 USB Device Interrupt Enable register (USBDevIntEn - 0x5000 C204)
11.10.2.4 USB Device Interrupt Clear register (USBDevIntClr - 0x5000 C208)
TxENDPKT
31
23
15
31
7
-
-
-
-
Description
Endpoints realized. Set when Realize Endpoint register (USBReEp) or MaxPacketSize
register (USBMaxPSize) is updated and the corresponding operation is completed.
Error Interrupt. Any bus error interrupt from the USB device. Refer to
“Read Error Status (Command: 0xFB, Data: read 1 byte)” on page 249
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Value
0
1
Writing a one to a bit in this register enables the corresponding bit in USBDevIntSt to
generate an interrupt on one of the interrupt lines when set. By default, the interrupt is
routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME
interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of
USBDevIntPri. USBDevIntEn is a read/write register.
Writing one to a bit in this register clears the corresponding bit in USBDevIntSt. Writing a
zero has no effect.
Remark: Before clearing the EP_SLOW or EP_FAST interrupt bits, the corresponding
endpoint interrupts in USBEpIntSt should be cleared.
USBDevIntClr is a write-only register.
ENDPKT
Rx
30
22
14
30
Description
No interrupt is generated.
An interrupt will be generated when the corresponding bit in the Device
Interrupt Status (USBDevIntSt) register
interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either
the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP
interrupt line by changing the value of USBDevIntPri.
6
-
-
-
-
All information provided in this document is subject to legal disclaimers.
CDFULL
29
21
13
29
5
-
-
-
-
Rev. 2 — 19 August 2010
CCEMPTY
28
20
12
28
4
-
-
-
-
DEV_STAT
Chapter 11: LPC17xx USB device controller
(Table
27
19
27
11
3
-
-
-
-
192) is set. By default, the
EP_SLOW
26
18
10
26
2
-
-
-
-
Section 11.12.9
EP_FAST
ERR_INT
25
17
25
UM10360
9
1
-
-
-
© NXP B.V. 2010. All rights reserved.
Reset value
0
0
NA
Reset value
0
EP_RLZED
FRAME
224 of 840
24
16
24
8
0
-
-
-