LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 800
LPC1769FBD100,551
Manufacturer Part Number
LPC1769FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.OM11043.pdf
(79 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
4.LPC1769FBD100551.pdf
(66 pages)
Specifications of LPC1769FBD100,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
100-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4966
935290522551
935290522551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1769FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10360
User manual
Should Be Zero or Preserved (SBZP) — Write as 0, or all 0s for bit fields, by software,
or preserved by writing the same value back that has been previously read from the same
field on the same processor.
Thread-safe — In a multi-tasking environment, thread-safe functions use safeguard
mechanisms when accessing shared resources, to ensure correct operation without the
risk of shared access conflicts.
Thumb instruction — One or two halfwords that specify an operation for a processor to
perform. Thumb instructions must be halfword-aligned.
Unaligned — A data item stored at an address that is not divisible by the number of bytes
that defines the data size is said to be unaligned. For example, a word stored at an
address that is not divisible by four.
Unpredictable (UNP) — You cannot rely on the behavior. Unpredictable behavior must
not represent security holes. Unpredictable behavior must not halt or hang the processor,
or any parts of the system.
Warm reset — Also known as a core reset. Initializes the majority of the processor
excluding the debug controller and debug logic. This type of reset is useful if you are using
the debugging features of a processor.
WA — See Write-allocate.
WB — See Write-back.
Word — A 32-bit data item.
Write — Writes are defined as operations that have the semantics of a store. Writes
include the Thumb instructions STM, STR, STRH, STRB, and PUSH.
Write-allocate (WA) — In a write-allocate cache, a cache miss on storing data causes a
cache line to be allocated into the cache.
Write-back (WB) — In a write-back cache, data is only written to main memory when it is
forced out of the cache on line replacement following a cache miss. Otherwise, writes by
the processor only update the cache. This is also known as copyback.
Write buffer — A block of high-speed memory, arranged as a FIFO buffer, between the
data cache and main memory, whose purpose is to optimize stores to main memory.
Write-through (WT) — In a write-through cache, data is written to main memory at the
same time as the cache is updated.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 34: Appendix: Cortex-M3 user guide
UM10360
© NXP B.V. 2010. All rights reserved.
800 of 840
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