LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 554

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 500: QEI Interrupt Status register (QEIINTSTAT - address 0x400B CFE0) bit description
Table 501: QEI Interrupt Set register (QEISET - address 0x400B CFEC) bit description
UM10360
User manual
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
31:13
Bit
0
1
2
3
4
5
6
7
8
9
Symbol
INX_Int
TIM_Int
VELC_Int
DIR_Int
ERR_Int
ENCLK_Int
POS0_Int
POS1_Int
POS2_Int
REV_Int
POS0REV_Int
POS1REV_Int
POS2REV_Int
-
Symbol
INX_Int
TIM_Int
VELC_Int
DIR_Int
ERR_Int
ENCLK_Int
POS0_Int
POS1_Int
POS2_Int
REV_Int
26.6.4.1 QEI Interrupt Status register (QEIINTSTAT)
26.6.4.2 QEI Interrupt Set register (QEISET - 0x400B CFEC)
26.6.4 Interrupt registers
This register provides the status of the encoder interface and the current set of interrupt
sources that are asserted to the controller. Bits set to 1 indicate the latched events that
have occurred; a zero bit indicates that the event in question has not occurred. Writing a 0
to a bit position clears the corresponding interrupt.
Writing a one to a bit in this register sets the corresponding bit in the QEI Interrupt Status
register (QEISTAT).
Description
Indicates that an index pulse was detected.
Indicates that a velocity timer overflow occurred
Indicates that captured velocity is less than compare velocity.
Indicates that a change of direction was detected.
Indicates that an encoder phase error was detected.
Indicates that and encoder clock pulse was detected.
Indicates that the position 0 compare value is equal to the current position.
Indicates that the position 1compare value is equal to the current position.
Indicates that the position 2 compare value is equal to the current position.
Indicates that the index compare value is equal to the current index count.
Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set
and the REV_Int is set.
Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set
and the REV_Int is set.
Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set
and the REV_Int is set.
reserved
Description
Indicates that an index pulse was detected.
Indicates that a velocity timer overflow occurred
Indicates that captured velocity is less than compare velocity.
Indicates that a change of direction was detected.
Indicates that an encoder phase error was detected.
Indicates that and encoder clock pulse was detected.
Indicates that the position 0 compare value is equal to the current position.
Indicates that the position 1compare value is equal to the current position.
Indicates that the position 2 compare value is equal to the current position.
Indicates that the index compare value is equal to the current index count.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 26: LPC17xx Quadrature Encoder Interface (QEI)
UM10360
© NXP B.V. 2010. All rights reserved.
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0
Reset
value
0
0
0
0
0
0
0
0
0
0
0
0
Reset
value
0
0
0
0
0
0
0
0
0